A vector distribution method for operation of a power amplifier of a wireless transmitter including receiving, by a first amplifier circuit, a first input vector and a second input vector. The first input vector includes data derived from an input signal of the wireless transmitter and the second input vector includes other data derived from the input signal of the wireless transmitter. The method includes, in response to receiving the input signal, instructing the first amplifier circuit to output an output signal at a high voltage.

A data formatting module of a low voltage drive circuit (LVDC) includes a sample and hold circuit, an interpreter, a first buffer, a digital to digital converter circuit, and a data packeting circuit. The sample and hold circuit is operable to sample and hold an n-bit digital value of filtered digital data to produce an n-bit sampled digital data value. The interpreter is operable to convert the n-bit sampled digital data value into interpreted n-bit sampled digital data. The interpreter is operable to write the interpreted n-bit sampled digital data into the first buffer in accordance with a write clock until a digital word is formed. The digital to digital converter circuit is operable to format the digital word to produce a formatted digital word. The data packeting circuit is operable to generate a data packet from the formatted digital word and output the data packet as received digital data.

A data slicer for converting an envelope signal of an amplitude-modulated wave into a binary signal, comprises: an average level generation circuit configured to generate an average level of the envelope signal by averaging the envelope signal per time; a fixed voltage value generation circuit configured to generate a fixed voltage value; a reference level generation circuit configured to generate a reference level in accordance with the fixed voltage value and the average level of the envelope signal; and a comparison circuit configured to compare a signal level of the envelope signal with the reference level to output a result of the comparison as the binary signal.

A radio frequency (RF) transmitter including a switched-capacitor digital-to-analog converter (SC-DAC) configured to selectively generate a first RF output signal having a first output power control range or a second RF output signal having a second output power control range from input signals received through a plurality of lines may be provided.

A signal processing chip includes: a receiving module, configured to receive a WLAN analog baseband signal from a baseband chip; an analog-to-digital conversion module, configured to convert the WLAN analog baseband signal into a WLAN digital baseband signal; a processing module, configured to process the WLAN digital baseband signal into a WLAN analog intermediate frequency signal; and a sending module, configured to send the WLAN analog intermediate frequency signal to a radio frequency processing apparatus.

Systems, methods and computer software are disclosed for providing 2G/3G communication over 4G/5G distributed unit (DU) in a virtual Radio Access Network (RAN) architecture.

Provided is a receiver device including a first A/D converter (203), a second A/D converter (204), an amplifier (205) which is provided at a previous stage of the second A/D converter (204), and a digital signal processing unit (207). The digital signal processing unit (207) includes an amplitude comparison unit (211) configured to compare an amplitude of a digital signal output from the first A/D converter (203) and an amplitude of a digital signal output from the second A/D converter (204) to make a determination, and to output a determination result, and a selector (212) configured to select one of the digital signal output from the first A/D converter (203) or the digital signal output from the second A/D converter (204) based on the determination result.

An electronic device comprises a first circuit portion comprising one or more components, including a first counter, which are clocked by a first clock signal. The first circuit portion is arranged to receive a data stream comprising a plurality of data signals. A second circuit portion comprises one or more components clocked by a second clock signal and a second counter not clocked by the second clock signal. The first clock signal is not synchronised to the second clock signal. The second circuit portion is arranged to: receive samples of the data stream from the first circuit portion at a sample rate and to time-stamp each received sample with a count value of the second counter. The second circuit portion increments the count value of the second counter by a predetermined increment value for each received sample.

A radio frequency identification (RFID) system includes an array of antennas to distinguish line-of-sight (LOS) paths from non-line-of-sight (NLOS) paths. The distance between adjacent antennas in the array of antennas is less than half the wavelength of the radio frequency (RF) signal of the system. Each antenna in the antenna array is also digitally controlled to change relative phase difference among the antennas, thereby allowing digital steering of the array of antennas across angles of arrival (AOAs) between 0 and π. The digital steering generates a plot of signal amplitudes as a function of AOAs. LOS paths are distinguished from NLOS paths based on the shapes (e.g., depth, gradient, etc.) of local extremes (e.g., maxima or minima) in the plot.

In one embodiment an apparatus includes: a mixer to downconvert a radio frequency (RF) spectrum including at least a first RF signal of a first channel of interest and a second RF signal of a second channel of interest to at least a first second frequency signal and a second second frequency signal; a first digitizer to digitize the first second frequency signal to a first digitized signal, the first digitizer configured to operate as a low-pass analog-to-digital converter (ADC); a second digitizer to digitize the second second frequency signal to a second digitized signal, the second digitizer configured to operate as a band-pass ADC; and a digital processor to digitally process the first digitized signal and the second digitized signal.