In a transmitter there is a distributor and assembly bank into which a predetermined quantity of an input payload from a source is repeatedly written according to a first distributor permutation to create as many input vectors as there are electromagnetic propagation pathways. A staging bank exists into which each input vector available from the assembly bank are repeatedly written according to a second distributor permutation. A presentation bank exists into which each input vector available from the staging bank are repeatedly written according to a third distributor permutation. One or more encoders repeatedly encode input vectors from the presentation bank; there being as many encoders as electromagnetic propagation pathways, and each encoder makes available each encoded ordered series of output levels for communication over the pathways. The banks and encoders are in up to four timing domains. A corresponding receiver, decoder, and reception, staging and disassembly banks and a sink are at the end of the pathways.

A three-level encoding transmitter is disclosed in which a transmitter circuit is configured to receive an input data signal including binary data and transmit an encoded data signal. The transmitter circuit can include an inverter circuit configured transmit first and second voltages for each logical level of the binary data. A transmission control circuit can cause the inverter circuit to transmit the voltages or deactivate the inverter circuit based on a first control signal. The transmitter circuit can further include an idle circuit configured to transmit an idle voltage between the first and second voltages when there is no data transmission. The idle circuit may transmit the idle voltage based on a second control signal. The first and second control signals may be configured to only be active when the other is inactive.

A three-level encoding transmitter is disclosed in which a transmitter circuit is configured to receive an input data signal including binary data and transmit an encoded data signal. The transmitter circuit can include an inverter circuit configured transmit first and second voltages for each logical level of the binary data. A transmission control circuit can cause the inverter circuit to transmit the voltages or deactivate the inverter circuit based on a first control signal. The transmitter circuit can further include an idle circuit configured to transmit an idle voltage between the first and second voltages when there is no data transmission. The idle circuit may transmit the idle voltage based on a second control signal. The first and second control signals may be configured to only be active when the other is inactive.

In an integrated circuit, a first current source is coupled between a first supply voltage and a first node. An output stage includes a first current steering PMOS transistor coupled to the first node, a first current steering NMOS transistor including a first current electrode coupled to the first current steering PMOS transistor at a second node, a second current steering PMOS coupled to the first node, and a second current steering NMOS transistor including a first current electrode coupled to the second current steering PMOS transistor at a third node. Voltage at the second node is used to drive a gate of the second current steering PMOS transistor, and voltage at the third node is used to drive a gate of the first current steering PMOS transistor. First and second programmable slew rate pre-drivers provide outputs to the gates of the first and second current steering NMOS transistors, respectively.

In an integrated circuit, a first current source is coupled between a first supply voltage and a first node. An output stage includes a first current steering PMOS transistor coupled to the first node, a first current steering NMOS transistor including a first current electrode coupled to the first current steering PMOS transistor at a second node, a second current steering PMOS coupled to the first node, and a second current steering NMOS transistor including a first current electrode coupled to the second current steering PMOS transistor at a third node. Voltage at the second node is used to drive a gate of the second current steering PMOS transistor, and voltage at the third node is used to drive a gate of the first current steering PMOS transistor. First and second programmable slew rate pre-drivers provide outputs to the gates of the first and second current steering NMOS transistors, respectively.

A front-end circuit includes an antenna connection terminal, a selection terminal, and a selection terminal, a switching circuit including a common terminal and selection terminals, a receive filter configured to pass a radio-frequency signal in Band B, a signal path connecting the selection terminal and the selection terminal and including the receive filter, a signal path connecting the selection terminal and the selection terminal and defining and functioning as a bypass path without any filter, and a filter coupled between the antenna connection terminal and the common terminal and configured to pass a first frequency range group including Band B.

A package or a chip including a linear amplifier and a power amplifier is provided, wherein the linear amplifier is configured to receive an envelope tracking signal to generate an amplified envelope tracking signal, the power amplifier is supplied by an envelope tracking supply voltage comprising a DC supply voltage and the amplified envelope tracking signal, and the power amplifier is configured to receive an input signal to generate an output signal.

A package or a chip including a linear amplifier and a power amplifier is provided, wherein the linear amplifier is configured to receive an envelope tracking signal to generate an amplified envelope tracking signal, the power amplifier is supplied by an envelope tracking supply voltage comprising a DC supply voltage and the amplified envelope tracking signal, and the power amplifier is configured to receive an input signal to generate an output signal.

A filter device configured to directly connect to a differential power amplifier of a transmit chain circuit. The filter device may include a transformer and a filter configured as a half lattice equivalent topology and having a single-ended output. The filter may be a lattice filter configured as a full lattice topology or a lattice equivalent filter configured as a half lattice equivalent topology. The filter includes a first branch having a first impedance network of one or more first impedance elements and a second branch having a second impedance network of one or more second impedance elements. The single-ended output of the filter device may connect to an antenna switch that is in turn connected to an antenna.

A filter device configured to directly connect to a differential power amplifier of a transmit chain circuit. The filter device may include a transformer and a filter configured as a half lattice equivalent topology and having a single-ended output. The filter may be a lattice filter configured as a full lattice topology or a lattice equivalent filter configured as a half lattice equivalent topology. The filter includes a first branch having a first impedance network of one or more first impedance elements and a second branch having a second impedance network of one or more second impedance elements. The single-ended output of the filter device may connect to an antenna switch that is in turn connected to an antenna.