A control device may comprise a primary radio circuit for receiving radio-frequency signals via an antenna, and a secondary radio circuit for waking up the primary radio circuit when a radio-frequency signal is presently being transmitted by an external device. The control device may include a control circuit that may be coupled to the primary radio circuit, and may control the primary radio circuit into a sleep mode. The secondary radio circuit may generate a first control signal indicating that the radio-frequency signal is presently being transmitted by the external device. The control circuit may wake up the primary radio circuit from the sleep mode in response to the secondary radio circuit generating the first control signal indicating that the radio-frequency signal is presently being transmitted by the external device.

A network communication device includes an input port configured to receive a downstream signal from a network, a first output port in communication with the input port and configured to receive a first reduced-power version of the signal received at the input port, one or more second output ports, and a converting circuit configured to receive a second reduced-power version of the signal received at the input port, down-convert a high-frequency portion thereof, and produce a down-converted signal. The one or more second output ports receive at least a portion of the down-converted signal.

A network communication device includes an input port configured to receive a downstream signal from a network, a first output port in communication with the input port and configured to receive a first reduced-power version of the signal received at the input port, one or more second output ports, and a converting circuit configured to receive a second reduced-power version of the signal received at the input port, down-convert a high-frequency portion thereof, and produce a down-converted signal. The one or more second output ports receive at least a portion of the down-converted signal.

A wireless transceiver for pairing and connecting to a plurality of wireless devices is provided. The wireless transceiver includes an antenna module, a power divider, and a plurality of RF chips. The antenna module is communicated to the wireless device. The power divider is electrically connected to the power divider, the RF chips are individually paired with one of the wireless devices, and each one of the RF chips and its paired wireless device have at least one same frequency channel, a wireless signal corresponding to the wireless device is sent and received through the power divider and the antenna module after the radio frequency (RF) chip and the wireless device are successfully paired.

A wireless transceiver for pairing and connecting to a plurality of wireless devices is provided. The wireless transceiver includes an antenna module, a power divider, and a plurality of RF chips. The antenna module is communicated to the wireless device. The power divider is electrically connected to the power divider, the RF chips are individually paired with one of the wireless devices, and each one of the RF chips and its paired wireless device have at least one same frequency channel, a wireless signal corresponding to the wireless device is sent and received through the power divider and the antenna module after the radio frequency (RF) chip and the wireless device are successfully paired.

A semiconductor chip includes a first wireless communication circuit, a local oscillator (LO) buffer, and an auxiliary path. The first wireless communication circuit has a signal path, wherein the signal path has a mixer input port and a signal node distinct from the mixer input port. The auxiliary path is used to electrically connect the LO buffer to the signal node of the signal path. The LO buffer is reused for a loop-back test function through the auxiliary path.

A semiconductor chip includes a first wireless communication circuit, a local oscillator (LO) buffer, and an auxiliary path. The first wireless communication circuit has a signal path, wherein the signal path has a mixer input port and a signal node distinct from the mixer input port. The auxiliary path is used to electrically connect the LO buffer to the signal node of the signal path. The LO buffer is reused for a loop-back test function through the auxiliary path.

A network communication device includes a first output port, a second output port, and a converting circuit. The first output port may be in communication with an input port and may be configured to receive a first reduced-power version of the signal received at an input port. The converting circuit may be configured to receive a second reduced-power version of the signal, down-convert a high-frequency portion thereof, and produce a down-converted signal. The first and the second reduced-power versions of the signals are in the same frequency band. The second output port receives at least a portion of the down-converted signal such that the high frequency portion of the second reduced power version of the signal is attenuated before the signal is transmitted to a subscriber device.

A network communication device includes a first output port, a second output port, and a converting circuit. The first output port may be in communication with an input port and may be configured to receive a first reduced-power version of the signal received at an input port. The converting circuit may be configured to receive a second reduced-power version of the signal, down-convert a high-frequency portion thereof, and produce a down-converted signal. The first and the second reduced-power versions of the signals are in the same frequency band. The second output port receives at least a portion of the down-converted signal such that the high frequency portion of the second reduced power version of the signal is attenuated before the signal is transmitted to a subscriber device.

A filter circuit includes: a division unit that divides an input signal and adds, to a tail end of a division block, of head data of the next division block, to generate an input block; a plurality of signal processing units that perform filtering of a feedback type on input blocks to generate output samples, and generate and output blocks; and a coupling unit that couples the output blocks. The signal processing unit outputs first output samples generated until a switching timing, and outputs second output samples generated by the signal processing unit after the timing. The switching timing is a timing within a period corresponding to the duplicated data, at which timing a difference between a first signal generated by the signal processing unit and a second signal generated by the signal processing unit is less than or equal to a threshold consecutively for a second data length.