Embodiments disclosed herein may be implemented in the form of a method or corresponding apparatus for receiving or transmitting network communications carried at acoustic wavelengths via an acoustic medium. The corresponding method or apparatus may include a gate-level digital hardware module communicatively coupled to a communications module and define therein logic blocks configured to perform respective primitive processing functions, sequences of the logic blocks being capable of processing data units in accordance with any of the multiple communications protocols on a data unit-by-data unit basis without reconfiguring. According to some embodiments, the gate-level digital hardware module may be configured to process a data unit in accordance with a first communications protocol by directing the data unit through a first sequence of logic blocks, and process a subsequent data unit in accordance with a second communications protocol by directing the subsequent data unit through a second of sequence logic blocks.

Embodiments disclosed herein may be implemented in the form of a method or corresponding apparatus for receiving or transmitting network communications carried at acoustic wavelengths via an acoustic medium. The corresponding method or apparatus may include a gate-level digital hardware module communicatively coupled to a communications module and define therein logic blocks configured to perform respective primitive processing functions, sequences of the logic blocks being capable of processing data units in accordance with any of the multiple communications protocols on a data unit-by-data unit basis without reconfiguring. According to some embodiments, the gate-level digital hardware module may be configured to process a data unit in accordance with a first communications protocol by directing the data unit through a first sequence of logic blocks, and process a subsequent data unit in accordance with a second communications protocol by directing the subsequent data unit through a second of sequence logic blocks.

A conformance testing method including: obtaining a testing symbol pattern in an optical signal; performing equalization compensation on the testing symbol pattern; generating a testing eye pattern; calculating a value of a first parameter based on the testing eye pattern and a noise enhancement coefficient, where the first parameter is used to determine a transmitter dispersion eye pattern closure degree of the optical transmitter; and when the value of the first parameter is less than or equal to a preset threshold, determining that conformance testing on the optical signal succeeds.

Methods, apparatus, and systems for communication over a C-PHY interface are disclosed. A transmitting device has a driver circuit configured to drive a three-wire bus in accordance with a symbol received at an input of the driver circuit, a pattern detector receives a sequence of symbols to be transmitted over the three-wire bus in a plurality of transmission symbol intervals, and a selection circuit responsive to a select signal provided by the pattern detector and configured to select between delayed and undelayed versions of a current symbol to drive the input of the driver circuit during a corresponding transmission symbol interval. The select signal may select the delayed version of the current symbol when a combination of the current symbol with an immediately preceding symbol cause the pattern detector to indicate a pattern match.

A conformance testing method including: obtaining a testing symbol pattern in an optical signal; performing equalization compensation on the testing symbol pattern; generating a testing eye pattern; calculating a value of a first parameter based on the testing eye pattern and a noise enhancement coefficient, where the first parameter is used to determine a transmitter dispersion eye pattern closure degree of the optical transmitter; and when the value of the first parameter is less than or equal to a preset threshold, determining that conformance testing on the optical signal succeeds.

Certain aspects of the present disclosure generally relate to a sampling circuit, such as a sampling circuit for a low-voltage differential signaling (LVDS) serializer/deserializer (SerDes) system. One example sampling circuit generally includes a latching circuit and a plurality of pass-gate transistors. The latching circuit includes differential inputs, differential outputs, a clocked input circuit coupled to the differential inputs, a first cross-coupled circuit coupled to the clocked input circuit, and a second cross-coupled circuit coupled to the first cross-coupled circuit, wherein the first and second cross-coupled circuits are coupled to the differential outputs of the latching circuit. Each pass-gate transistor is coupled between one of the differential inputs of the latching circuit and a corresponding differential input of the sampling circuit.

The present disclosure relates to an audio data transmission method and apparatus. The method includes: determining a frequency of sampling of audio data to be processed as a clock frequency of a first clock signal; determining a clock frequency of a second clock signal according to the clock frequency of the first clock signal, a number of slots of the audio data to be processed and a preset audio data occupied bit width; determining a duration of a high level in each cycle of the first clock signal according to the clock frequency of the second clock signal and the number of slots; and outputting the processed audio data according to a pulse code modulation (PCM) timing determined by the clock frequency of the first clock signal, the clock frequency of the second clock signal and the duration of the high level in each cycle of the first clock signal.

The present disclosure relates to an audio data transmission method and apparatus. The method includes: determining a frequency of sampling of audio data to be processed as a clock frequency of a first clock signal; determining a clock frequency of a second clock signal according to the clock frequency of the first clock signal, a number of slots of the audio data to be processed and a preset audio data occupied bit width; determining a duration of a high level in each cycle of the first clock signal according to the clock frequency of the second clock signal and the number of slots; and outputting the processed audio data according to a pulse code modulation (PCM) timing determined by the clock frequency of the first clock signal, the clock frequency of the second clock signal and the duration of the high level in each cycle of the first clock signal.

Embodiments disclosed herein may be implemented in the form of a method or corresponding apparatus for receiving or transmitting network communications carried at acoustic wavelengths via an acoustic medium. The corresponding method or apparatus may include a gate-level digital hardware module communicatively coupled to a communications module and define therein logic blocks configured to perform respective primitive processing functions, sequences of the logic blocks being capable of processing data units in accordance with any of the multiple communications protocols on a data unit-by-data unit basis without reconfiguring. According to some embodiments, the gate-level digital hardware module may be configured to process a data unit in accordance with a first communications protocol by directing the data unit through a first sequence of logic blocks, and process a subsequent data unit in accordance with a second communications protocol by directing the subsequent data unit through a second of sequence logic blocks.

Embodiments disclosed herein may be implemented in the form of a method or corresponding apparatus for receiving or transmitting network communications carried at acoustic wavelengths via an acoustic medium. The corresponding method or apparatus may include a gate-level digital hardware module communicatively coupled to a communications module and define therein logic blocks configured to perform respective primitive processing functions, sequences of the logic blocks being capable of processing data units in accordance with any of the multiple communications protocols on a data unit-by-data unit basis without reconfiguring. According to some embodiments, the gate-level digital hardware module may be configured to process a data unit in accordance with a first communications protocol by directing the data unit through a first sequence of logic blocks, and process a subsequent data unit in accordance with a second communications protocol by directing the subsequent data unit through a second of sequence logic blocks.