An eye pattern generator for generating an eye pattern of an input signal is provided. The eye pattern generator includes first and second comparators and a control circuit. The first comparator receives the input signal, a clock signal, and a first voltage and compares the input signal with the first voltage according to the clock signal to generate a first comparison signal. The second comparator receives the input signal, the clock signal, and a second voltage lower than the first voltage and compares the input signal with the second voltage according to the clock signal to generate a second comparison signal. The control circuit changes at least one of a level of the first voltage and a level of the second voltage according to the first and second comparison signals to form a region boundary between an open-eye region and a closed-eye region of the eye pattern.

A communication system is configured to use a pulse width modulation signal as transmission code among a plurality of nodes connected to a communication line. A master node includes a transmission transistor connected to the communication line, a detector configured to detect a variation in current during the on-period of the transmission transistor, and a communication circuit configured to determine the off-timing of the transmission transistor based on the timing of occurrence of the variation in current (i.e., the on-timing of a second transmission transistor provided in a slave node). For example, the communication circuit can be configured to determine the off-timing of the transmission transistor such that the simultaneously-on period TB of the transmission transistor and the second transmission transistor fulfills TB=(2n?1)/2f, where f is the frequency of EMI noise.

The present disclosure relates to an encoder and an encoding method thereof, as well as a decoder and a decoding method thereof, which can be used to reduce the number of wires necessary for data transmission and transmit more data at a faster speed with the same number of wires, thereby improving the efficiency of data transmission. The encoder may comprises two input terminals configured to receive two input signals simultaneously, each input terminal comprises a wire identifying a positive voltage and a wire identifying a negative voltage; and a plurality of output terminals, wherein each output terminal comprises a wire identifying a positive voltage and a wire identifying a negative voltage, a combination of the two input signals corresponds to one of the plurality of output terminals, and the output terminal to which the current combination of the two input signals corresponds is configured to output signals through the two wires of the output terminal.

An apparatus includes a transmitter circuit coupled to a termination resistor. The transmitter circuit generates a number of link pulses. A driver circuit is coupled to the transmitter circuit to control a dynamic range of the link pulses. A transformer couples the termination resistor via a transmission medium to a far-end transceiver. The driver circuit controls the dynamic range of the link pulses by providing complementary digital input signals to the transmitter circuit, and the complementary digital input signals include ramp sections.

An apparatus for generating an output signal, may comprise a signal path having an analog signal path portion having an analog magnitude droop, a digital signal path portion having a digital magnitude droop, a digital-to-analog converter for converting the digital input signal into the analog signal, a first digital compensation filter that compensates for the analog magnitude droop, and a second digital compensation filter that compensates for the digital magnitude droop, such that the first digital compensation filter and the second digital compensation filter together compensate for magnitude droop of the signal path to ensure a substantially flat passband response of the signal path.

An apparatus may include a delta-sigma modulator for quantization noise shaping of a digital signal, a digital-to-analog converter configured to generate an analog signal from the digital signal, and an amplifier configured to amplify the analog signal and powered from a charge pump, wherein the charge pump is configured to operate at a switching frequency approximately equal to a zero of a modulator noise transfer function of the delta-sigma modulator, such that the impact of charge pump noise on a total harmonic distortion noise of the apparatus is minimized

An apparatus may include a delta-sigma modulator for quantization noise shaping of a digital signal, a digital-to-analog converter configured to generate an analog signal from the digital signal, and an amplifier configured to amplify the analog signal and powered from a charge pump, wherein the charge pump is configured to operate at a switching frequency approximately equal to a zero of a modulator noise transfer function of the delta-sigma modulator, such that the impact of charge pump noise on a total harmonic distortion noise of the apparatus is minimized.

A receiver for a modulated signal of a communication system is disclosed. The receiver includes a demodulator to demodulate the received modulated symbols of a received signal into received soft-bits. The receiver also includes a hard-decision decoder that is configured to decode the received soft-bits into decoded bits. A feedback loop is included to provide feedback from the hard decision decoder to the demodulator. The feedback loop is configured to re-encode the decoded bits from the hard-decision decoder into re-encoded bits. The demodulator is further configured to iteratively demodulate the received modulated signal using an output of the feedback loop.

There is disclosed herein a circuitry system comprising first and second IC chips, configured or configurable such that; the first IC chip has an output terminal connected to receive an output signal from an output-signal unit of the first IC chip, the output-signal unit being connected between high and low voltage-reference sources of the first IC chip, the high and low voltage-reference sources being connected to respective high and low voltage-reference terminals of the first IC chip; and the second IC chip has an input terminal connected in a potential-divider arrangement between high and low voltage-reference terminals of the second IC chip, wherein: the high and low voltage-reference terminals of the first IC chip are respectively connected to the high and low voltage-reference terminals of the second IC chip; and the output terminal of the first IC chip is connected to the input terminal of the second IC chip.

Embodiments disclosed herein may be implemented in the form of a method or corresponding apparatus for receiving or transmitting network communications carried at acoustic wavelengths via an acoustic medium. The corresponding method or apparatus may include a gate-level digital hardware module communicatively coupled to a communications module and define therein logic blocks configured to perform respective primitive processing functions, sequences of the logic blocks being capable of processing data units in accordance with any of the multiple communications protocols on a data unit-by-data unit basis without reconfiguring. According to some embodiments, the gate-level digital hardware module may be configured to process a data unit in accordance with a first communications protocol by directing the data unit through a first sequence of logic blocks, and process a subsequent data unit in accordance with a second communications protocol by directing the subsequent data unit through a second of sequence logic blocks.

Embodiments disclosed herein may be implemented in the form of a method or corresponding apparatus for receiving or transmitting network communications carried at acoustic wavelengths via an acoustic medium. The corresponding method or apparatus may include a gate-level digital hardware module communicatively coupled to a communications module and define therein logic blocks configured to perform respective primitive processing functions, sequences of the logic blocks being capable of processing data units in accordance with any of the multiple communications protocols on a data unit-by-data unit basis without reconfiguring. According to some embodiments, the gate-level digital hardware module may be configured to process a data unit in accordance with a first communications protocol by directing the data unit through a first sequence of logic blocks, and process a subsequent data unit in accordance with a second communications protocol by directing the subsequent data unit through a second of sequence logic blocks.