Examples of backscatter systems, device, and techniques are described herein. Example backscatter devices may utilize CSS modulation to provide backscatter signals including CSS signals (e.g., LoRa packets). Utilizing CSS modulation may advantageously allow for backscatter communication over wide areas. Examples of backscatter devices described herein may toggle the impedance of the backscatter device between multiple (e.g., eight) impedances to reduce and/or eliminate higher order harmonic components in the backscatter signal (e.g., third and fifth harmonic components).

A method for ramping a switched capacitor power amplifier is disclosed, where the switched capacitor power amplifier comprises a plurality of capacitors in a capacitor bank, and where a number of the capacitors in the capacitor bank are activated. The method comprises changing the number of capacitors in the capacitor bank that are activated, maintaining the changed number of activated capacitors in the capacitor bank for a period of time, and repeating the changing and maintaining, where a length of the period of time is varied between at least two repetitions of the maintaining.

In one form, a spread spectrum clock generator includes an oscillator and a digital modulator. The oscillator has a control input for setting an output frequency, and an output for providing a clock output signal. The digital modulator is responsive to the clock output signal to provide a control code to the control input of the oscillator as a periodic signal with a plurality of discrete steps, wherein the digital modulator provides said control code at each of said plurality of discrete steps for substantially a predetermined time.

A switching converter, including an input interface for providing an input voltage, an output interface for providing at least one output voltage, a voltage conversion device for converting the provided input voltage into one of the at least one output voltage, and a clock generator for providing a working clock, the clock generator being configured in such a way that the clock generator provides a modulated basic clock as the working clock. A control unit including such a switching converter, and a method for operating such a switching converter, are also described.

An isolation system and isolation device are disclosed. An illustrative isolation device is disclosed to include a transmitter side and receiver side separated by an isolation material. One or more components of the transmitter side operate on a clock signal whereas one or more components of the receiver side operate on a scrambled clock signal. The scrambled clock signal is generated to have a different energy distribution than the clock signal and is also generated to have a dominant peak value that is lower than the dominant peak value of the clock signal.

An isolation system and isolation device are disclosed. An illustrative isolation device is disclosed to include a transmitter side and receiver side separated by an isolation material. One or more components of the transmitter side operate on a clock signal whereas one or more components of the receiver side operate on a scrambled clock signal. The scrambled clock signal is generated to have a different energy distribution than the clock signal and is also generated to have a dominant peak value that is lower than the dominant peak value of the clock signal.

A clock generation circuit includes a random number generator configured to generate random numbers according to a first probability distribution, a filter configured to output random numbers according to a second probability distribution, based on the random numbers according to the first probability distribution input thereto, and a variable delay circuit configured to modulate a clock signal input thereto by delaying edges of the clock signal by amounts corresponding to values of the random numbers according to the second probability distribution. Probability of a smallest number according to the second probability distribution is smaller than probability of the smallest number according to the first probability distribution, and probability of a largest number according to the second probability distribution is smaller than probability of the largest number according to the first probability distribution.

A clock generation circuit includes a random number generator configured to generate random numbers according to a first probability distribution, a filter configured to output random numbers according to a second probability distribution, based on the random numbers according to the first probability distribution input thereto, and a variable delay circuit configured to modulate a clock signal input thereto by delaying edges of the clock signal by amounts corresponding to values of the random numbers according to the second probability distribution. Probability of a smallest number according to the second probability distribution is smaller than probability of the smallest number according to the first probability distribution, and probability of a largest number according to the second probability distribution is smaller than probability of the largest number according to the first probability distribution.

A semiconductor device comprising interface logic for transmitting data bursts across an interface. The interface logic is arranged to transmit bursts of data across the interface such that the start of a burst of data is substantially aligned with a symbol interval (SI) boundary. The interface logic is further arranged to apply an offset to the SI boundary at the start of the burst of data.

A transmitter 1 comprises a clock generation portion 4, FIFO portion 6, and serial signal creation portion 7. The clock generation portion 4 performs modulation by spectrum spreading of a reference clock CK.sub.ref, and generates a first clock CK.sub.1 with a high modulation factor and a second clock CK.sub.2 with a low modulation factor. The FIFO portion 6 takes as inputs the first clock CK.sub.1 which has been output from the clock generation portion 4 to a data generation portion 2 and output from the data generation portion 2, a parallel data signal which has been synchronized with the first clock CK.sub.1 in the data generation portion 2 and output, and the second clock CK.sub.2 output from the clock generation portion 4, and synchronizes the parallel data signal P.sub.data with the second clock CK.sub.2 and outputs the parallel data signal P.sub.data. The serial signal creation portion 7 converts a parallel data signal PR.sub.data into a serial data signal S.sub.data.