A switch circuit and a high-speed multiplexer-demultiplexer are provided. The switch circuit includes an equalization module and an MOS transistor. A gate of the first MOS transistor is connected to an output terminal of the equalization module. An input terminal of the first MOS transistor is connected to a signal source. An output terminal of the first MOS transistor is connected to a subsequent circuit. The equalization module is configured to: supply a turning-on signal to the first MOS transistor in a case that an operation signal is acquired, to turn on the first MOS transistor; and generate a compensation signal for compensating an attenuation of the signal transmitted through the first MOS transistor, and apply the compensation signal to the gate of the first MOS transistor. The switch circuit operates in response to the operation signal.

Systems and methods for data multiplexing include or use a data serializer having a first set of four serializer outputs and a second set of four serializer outputs. The systems and methods also use or include a pair of 4 to 1 multiplexers each having four first multiplexer inputs and one first multiplexer outputs and a 2 to 1 multiplexer having two multiplexer inputs and one multiplexer output.

The disclosure relates to an overlapped multiplexing modulation method, apparatus, and system. An initial envelope waveform that is smooth in a time domain or frequency domain is generated based on design parameters; the initial envelope waveform is shifted in the time domain or frequency domain at a preset spectrum interval based on times of overlapped multiplexing, to obtain subcarrier envelope waveforms; an input digital signal sequence is converted into a positive-negative symbol sequence; each symbol in the positive-negative symbol sequence is multiplied by a subcarrier envelope waveform corresponding to the symbol, to obtain modulated envelope waveforms of subcarriers; the modulated envelope waveforms of the subcarriers are superimposed in the time domain or frequency domain, to obtain a time-domain or frequency-domain complex modulated envelope waveform; and the time-domain or frequency-domain complex modulated envelope waveform is transformed, to obtain a time-domain or frequency-domain complex modulated envelope waveform.

The disclosure relates to an overlapped multiplexing modulation method, apparatus, and system. An initial envelope waveform that is smooth in a time domain or frequency domain is generated based on design parameters; the initial envelope waveform is shifted in the time domain or frequency domain at a preset spectrum interval based on times of overlapped multiplexing, to obtain subcarrier envelope waveforms; an input digital signal sequence is converted into a positive-negative symbol sequence; each symbol in the positive-negative symbol sequence is multiplied by a subcarrier envelope waveform corresponding to the symbol, to obtain modulated envelope waveforms of subcarriers; the modulated envelope waveforms of the subcarriers are superimposed in the time domain or frequency domain, to obtain a time-domain or frequency-domain complex modulated envelope waveform; and the time-domain or frequency-domain complex modulated envelope waveform is transformed, to obtain a time-domain or frequency-domain complex modulated envelope waveform.

A system for limiting or diminishing current to unpowered Serializer/Deserializer (SerDes) circuitry is provided. The system comprises receiver input termination circuitry and a cold spare circuitry. The receiver input circuitry comprises a termination resistor and an N-type metal oxide silicon field effect transistor (MOSFET). The cold spare circuitry comprises a first MOSFET and a second MOSFET. When the system is powered on, an input current flows to the receiver input termination circuit to be discharged by the N-type MOSFET which is electrically connected to a ground. When the system is powered off, the input current flows to the cold spare circuitry to discharge the input current. Discharging electrons between the first MOSFET and the second MOSFET depends on the polarity of an accumulated voltage.

This application proposes multi-beam antenna systems using spherical lens are proposed, with high isolation between antenna ports and compatible to 22, 44, 88 MIMO transceivers. Several compact multi-band multi-beam solutions (with wideband operation, 40%+, in each band) are achieved by creating dual-band radiators movable on the track around spherical lens and by placing of lower band radiators between spherical lenses. By using of secondary lens for high band radiators, coupling between low band and high band radiators is reduced. Beam tilt range and side lobe suppression are improved by special selection of phase shift and rotational angle of radiators. Resultantly, a wide beam tilt range (0-40 degree) is realized in proposed multi-beam antenna systems. Each beam can be individually tilted. Based on proposed single- and multi-lens antenna solutions, cell coverage improvements and stadium tribune coverage optimization are also achieved, together with interference reduction.

A system for serializing input data signals and generating an output data signal includes a FIFO memory that launches the input data signals at different phases of a clock signal. The system further includes multiple stages of a serializer circuit, and each stage of the serializer circuit receives a clock signal. Each successive stage includes half the number of serializer circuits that are included in the previous stage, and each successive stage is clocked by a clock signal that transitions at twice the frequency of the previous stage clock signal. The serializer circuits that belong to a single stage receive the clock signal with different phase. The phase and frequency of clock signals of serializer stages are adjusted such that a launched input data signal is outputted as the output data signal. Further, a critical path for each serializer circuit is equal to full clock cycle of the clock signal.

This application proposes multi-beam antenna systems using spherical lens are proposed, with high isolation between antenna ports and compatible to 22, 44, 88 MIMO transceivers. Several compact multi-band multi-beam solutions (with wideband operation, 40%+, in each band) are achieved by creating dual-band radiators movable on the track around spherical lens and by placing of lower band radiators between spherical lenses. By using of secondary lens for high band radiators, coupling between low band and high band radiators is reduced. Beam tilt range and side lobe suppression are improved by special selection of phase shift and rotational angle of radiators. Resultantly, a wide beam tilt range (0-40 degree) is realized in proposed multi-beam antenna systems. Each beam can be individually tilted. Based on proposed single- and multi-lens antenna solutions, cell coverage improvements and stadium tribune coverage optimization are also achieved, together with interference reduction.

Various aspects provide for a multiplexer for high-speed serial links. For example, a system can include a first stage data path multiplexer circuit and a second stage data path multiplexer circuit. The first stage data path multiplexer circuit comprises a first inverter circuit to select a first data signal from a set of data signals and a second inverter circuit to select a second data signal from the set of data signals. The first inverter circuit comprises a first set of inverters and a first set of transmission gates. The second inverter circuit comprises a second set of inverters and a second set of transmission gates. The second stage data path multiplexer circuit is configured as a third inverter circuit to select the first data signal or the second data signal as an output data signal. The third inverter circuit comprises a third set of inverters and a third set of transmission gates.

A system for serializing input data signals and generating an output data signal includes a FIFO memory that launches the input data signals at different phases of a clock signal. The system further includes multiple stages of a serializer circuit, and each stage of the serializer circuit receives a clock signal. Each successive stage includes half the number of serializer circuits that are included in the previous stage, and each successive stage is clocked by a clock signal that transitions at twice the frequency of the previous stage clock signal. The serializer circuits that belong to a single stage receive the clock signal with different phase. The phase and frequency of clock signals of serializer stages are adjusted such that a launched input data signal is outputted as the output data signal. Further, a critical path for each serializer circuit is equal to full clock cycle of the clock signal.