A system for serializing input data signals and generating an output data signal includes a FIFO memory that launches the input data signals at different phases of a clock signal. The system further includes multiple stages of a serializer circuit, and each stage of the serializer circuit receives a clock signal. Each successive stage includes half the number of serializer circuits that are included in the previous stage, and each successive stage is clocked by a clock signal that transitions at twice the frequency of the previous stage clock signal. The serializer circuits that belong to a single stage receive the clock signal with different phase. The phase and frequency of clock signals of serializer stages are adjusted such that a launched input data signal is outputted as the output data signal. Further, a critical path for each serializer circuit is equal to full clock cycle of the clock signal.

A data communication device communicating with other devices via multiple communication paths includes a transmission unit and a reception unit. The transmission unit is configured to receive a packet containing header information and data, to output the header information to each of the communication paths, to divide the data into multiple data pieces, and to output the data pieces to the respective communication paths. The reception unit is configured to receive header information and a data piece for each of the communication paths, and to reconstruct a packet from the header information and the data piece received from each of the communication paths. In reconstructing the packet, the reception unit adjusts, for each of the communication paths, output timing of the data piece, based on the header information.

A system for limiting or diminishing current to unpowered Serializer/Deserializer (SerDes) circuitry is provided. The system comprises receiver input termination circuitry and a cold spare circuitry. The receiver input circuitry comprises a termination resistor and an N-type metal oxide silicon field effect transistor (MOSFET). The cold spare circuitry comprises a first MOSFET and a second MOSFET. When the system is powered on, an input current flows to the receiver input termination circuit to be discharged by the N-type MOSFET which is electrically connected to a ground. When the system is powered off, the input current flows to the cold spare circuitry to discharge the input current. Discharging electrons between the first MOSFET and the second MOSFET depends on the polarity of an accumulated voltage.

A true single-phase clocked multiplexer for outputting one of a plurality of input signals in synchronization with a clock signal and as selected by at least one select signal is provided. The multiplexer includes first transistors, second transistors, a first node between the first transistors, a second node between the second transistors, a third node coupled to the first node by one of the first transistors and to the second node by one of the second transistors, and a pre-charge transistor to couple the third node to a first voltage level. The first transistors are coupled to the first voltage level and configured to turn on in response to a gate voltage of a second voltage level different from the first voltage level. The second transistors are coupled to the second voltage level and configured to turn on in response to a gate voltage of the first voltage level.

A true single-phase clocked multiplexer for outputting one of a plurality of input signals in synchronization with a clock signal and as selected by at least one select signal is provided. The multiplexer includes first transistors, second transistors, a first node between the first transistors, a second node between the second transistors, a third node coupled to the first node by one of the first transistors and to the second node by one of the second transistors, and a pre-charge transistor to couple the third node to a first voltage level. The first transistors are coupled to the first voltage level and configured to turn on in response to a gate voltage of a second voltage level different from the first voltage level. The second transistors are coupled to the second voltage level and configured to turn on in response to a gate voltage of the first voltage level.

A system for serializing input data signals and generating an output data signal includes a FIFO memory that launches the input data signals at different phases of a clock signal. The system further includes multiple stages of a serializer circuit, and each stage of the serializer circuit receives a clock signal. Each successive stage includes half the number of serializer circuits that are included in the previous stage, and each successive stage is clocked by a clock signal that transitions at twice the frequency of the previous stage clock signal. The serializer circuits that belong to a single stage receive the clock signal with different phase. The phase and frequency of clock signals of serializer stages are adjusted such that a launched input data signal is outputted as the output data signal. Further, a critical path for each serializer circuit is equal to full clock cycle of the clock signal.

A serializer circuit may include a recovery circuit, an adjusting circuit, and a multiplexer circuit. The recovery circuit may be configured to receive a first data signal at a first frequency, to generate a first clock signal at the first frequency using the first data signal, and to retime the first data signal based on the first clock signal to generate a retimed first data signal. The adjusting circuit may be configured to receive a second data signal and retime the second data signal based on the first clock signal to generate a retimed second data signal. The multiplexer circuit may be configured to multiplex the retimed first data signal and the retimed second data signal.

The disclosure relates to an overlapped multiplexing modulation method, apparatus, and system. An initial envelope waveform that is smooth in a time domain or frequency domain is generated based on design parameters; the initial envelope waveform is shifted in the time domain or frequency domain at a preset spectrum interval based on times of overlapped multiplexing, to obtain subcarrier envelope waveforms; an input digital signal sequence is converted into a positive-negative symbol sequence; each symbol in the positive-negative symbol sequence is multiplied by a subcarrier envelope waveform corresponding to the symbol, to obtain modulated envelope waveforms of subcarriers; the modulated envelope waveforms of the subcarriers are superimposed in the time domain or frequency domain, to obtain a time-domain or frequency-domain complex modulated envelope waveform; and the time-domain or frequency-domain complex modulated envelope waveform is transformed, to obtain a time-domain or frequency-domain complex modulated envelope waveform.

The disclosure relates to an overlapped multiplexing modulation method, apparatus, and system. An initial envelope waveform that is smooth in a time domain or frequency domain is generated based on design parameters; the initial envelope waveform is shifted in the time domain or frequency domain at a preset spectrum interval based on times of overlapped multiplexing, to obtain subcarrier envelope waveforms; an input digital signal sequence is converted into a positive-negative symbol sequence; each symbol in the positive-negative symbol sequence is multiplied by a subcarrier envelope waveform corresponding to the symbol, to obtain modulated envelope waveforms of subcarriers; the modulated envelope waveforms of the subcarriers are superimposed in the time domain or frequency domain, to obtain a time-domain or frequency-domain complex modulated envelope waveform; and the time-domain or frequency-domain complex modulated envelope waveform is transformed, to obtain a time-domain or frequency-domain complex modulated envelope waveform.

A network system includes a first device and a second device coupled to each other that mux and demux data for LSL to HSL transitions. The muxing and demuxing function in the first and second device, respectively, use timing logic from an existing training protocol, such as link training (LT). Although LT is used for establishing links between two chips, and has no provision for maintaining port coherency for port-specific input data on one chip to port-specific output data on another chip, the LT does have a uniquely identifiable logic transition in a known data pattern used for LT that can be multi-purposed for syncing the muxing and demuxing of the two interfaced chips, using a predetermined port sequence on both chips to maintain coherency of port-specific data.