A modular system uses point-to-point communication between field-programmable gate arrays (FPGAs) on a control module and each port module, respectively, to manage basic module functions, such as power, environmental monitoring, and health checks on the modules and their components. This allows a chassis to be managed without fully powering each card first, frees processors on the modules from having to perform health checks, allows dedicated resources to rapidly monitor the health of each card, and prevents one bad card from disabling management of all cards.

Disclosed is a synchronized adaptive infrastructure (SAIN) network. Switches, synchronized nodes, and persistent connections can be used. Also described are methods and apparatus for the following functions: disjoint partitioning; data aggregation and disaggregation; interfacing with packet-based networks; bandwidth management; use of control vectors for security, addressing, error control, routing, etc. Synchronized networks are disclosed which enable fast connection set up and release in a tiered hierarchy of circuit switched nodes. Methods of synchronizing and transforming data streams are disclosed, as well as overcoming Doppler, environmental, and frequency offset effects.

An ethernet-based communication system is provided. The communication system comprises: a first unit configured to generate a reference clock signal by using an input first ethernet signal, multiplex the first ethernet signal and a second ethernet signal in response to the reference clock signal, and output the multiplexed ethernet signals; a second unit configured to generate the reference clock signal by using the multiplexed ethernet signals, separate the second ethernet signal from the multiplexed ethernet signals in response to the reference clock signal, and output the first ethernet signal; and a transmission medium for connecting the first and second units and transmitting the multiplexed ethernet signals from the first unit to the second unit.

A system and method of receiving HDLC communications is disclosed. The system measures the pulse width of the incoming signal and converts each pulse into a series of bits, based on its pulse width. In this way, the reception of the HDLC communication is not dependent on any particular clock rate and is adaptable. The system takes advantages of the fact that the flag is a string of six consecutive bits that are all 1. Thus, the longest positive pulse width may be used to determine the bit rate. This allows the system to operate over a very broad range of data rates.

Various examples of the present disclosure relate to a transmitter apparatus, device, method, and computer program, to a receiver apparatus, device, method, and computer program, and to corresponding source and destination devices and communication devices. The transmitter apparatus comprises a plurality of ports for data to be transmitted to a destination device, with each port being associated with a transmission data rate. The transmitter apparatus comprises processing circuitry configured to obtain data to be transmitted to the destination device via the plurality of ports. The processing circuitry is configured to multiplex the data to be transmitted to the destination device according to a weighted round-robin scheme to generate a multiplexed data stream. The weights of the weighted round-robin scheme are based on the transmission data rate of the respective port the data is obtained over. The processing circuitry is configured to transmit the multiplexed data stream to the destination device.

The present disclosure provides a synchronized time division multiple access (TDMA) network is disclosed. The synchronized TDMA network includes computing devices and a central control system. The central control system monitors transmission of data packets between the computing devices and the central control system. The central control system assigns a communication slot to each of the computing devices, for synchronizing the central control system with the computing devices. The central control system determines a communication schedule for each of the computing devices. The communication schedule defines a direction, computing devices involved, and types of data transactions occurring at a predetermined time frame. The central control system transmits a data packet to each of the computing devices at predefined intervals for aligning a timing parameter of communication of each of the computing devices and the central control system.