Aspects of the invention include using a cyclic redundancy code (CRC) multiple-input signature register (MISR) for early warning and fail detection. Received bits are monitored at a receiver for transmission errors. The monitoring includes receiving frames of bits that are a subset of frames of bits used by the transmitter to generate a multi-frame CRC. At least one of the received frames of bits includes payload bits and a source single check bit not included in the multi-frame CRC. It is determined whether a transmission error has occurred in the received frames of bits. The determining includes generating a calculated single check bit based at least in part on bits in the received frames of bits, and comparing the received source single check bit to the calculated single check bit. An error indication is transmitted to the transmitter if they don't match.

Provided by the present invention are a data transmission method and a terminal, and the method comprises: acquiring data to be sent comprising N data frames; acquiring a bit sequence of an i.sup.th data frame; sending X waveform sequences corresponding to bits in the bit sequence of the i.sup.th data frame; detecting a level change of a receiving port after completion of sending the X waveform sequences; determining Y waveform sequences of received data; determining a bit sequence of the received data; acquiring a bit sequence of an (i+1).sup.th data frame when the bit sequence at least comprises a flag bit for at least indicating success of receiving data; sending Z waveform sequences corresponding to bits in the bit sequence of the (i+1).sup.th data frame until all the N data frames of the data to be sent are sent.

Embodiments of a bus interface system are disclosed. The bus interface system includes a master bus controller and a slave bus controller coupled to a bus line. The master bus controller and the slave bus controller are configured to perform read operations using error codes and error checks. For example, the error codes may be cyclic redundancy codes (CRC). In this manner, accuracy is ensured during communications between the slave bus controller and the master bus controller.

Provided by the present invention are a data transmission method and a terminal, and the method comprises: acquiring data to be sent comprising N data frames; acquiring a bit sequence of an i.sup.th data frame; sending X waveform sequences corresponding to bits in the bit sequence of the i.sup.th data frame; detecting a level change of a receiving port after completion of sending the X waveform sequences; determining Y waveform sequences of received data; determining a bit sequence of the received data; acquiring a bit sequence of an (i+1).sup.th data frame when the bit sequence at least comprises a flag bit for at least indicating success of receiving data; sending Z waveform sequences corresponding to bits in the bit sequence of the (i+1).sup.th data frame until all the N data frames of the data to be sent are sent.

The disclosure relates to a method for serially transmitting a frame from a transmitter to at least one receiver by means of a bus line, as well as a subscriber station for a bus system. According to said method, stuff bits are inserted into the frame by the transmitter according to a predetermined rule in order to generate additional signal edges, and/or said stuff bits are removed again by the receiver when evaluating the frame, at least one item of information relating to a subsection of the frame additionally being added, and transmitted, outside of this subsection, and said subsection containing a predetermined sequence of bit values.

First data is received on a plurality of data lanes of a physical link and a stream signal corresponding to the first data is received on a stream lane identifying a type of the first data. A first instance of an error detection code of a particular type is identified in the first data. Second data is received on at least a portion of the plurality of data lanes and a stream signal corresponding to the second data is received on the stream lane identifying a type of the second data. A second instance of the error detection code of the particular type is identified in the second data. The stream lane is another one of the lanes of the physical link and, in some instance, the type of the second data is different from the type of the first data.

Embodiments of a bus interface system are disclosed. In one embodiment, the bus interface system includes a master bus controller and a slave bus controller coupled to a bus line. The master bus controller is configured to generate a first set of data pulses along the bus line representing a payload segment. The slave bus controller is configured to decode the first set of data pulses representing the payload segment into a decoded payload segment. The slave bus controller is then configured to perform a first error check on the decoded payload segment. Furthermore, the slave bus controller is configured to generate an acknowledgment signal along the bus line so that the acknowledgement signal indicates that the decoded payload segment passed the first error check. In this manner, the master bus controller can determine that the slave bus controller received an accurate copy of the payload segment.

Aspects of the invention include using a cyclic redundancy code (CRC) multiple-input signature register (MISR) for early warning and fail detection. Received bits are monitored at a receiver for transmission errors. The monitoring includes receiving frames of bits that are a subset of frames of bits used by the transmitter to generate a multi-frame CRC. At least one of the received frames of bits includes payload bits and a source single check bit not included in the multi-frame CRC. It is determined whether a transmission error has occurred in the received frames of bits. The determining includes generating a calculated single check bit based at least in part on bits in the received frames of bits, and comparing the received source single check bit to the calculated single check bit. An error indication is transmitted to the transmitter if they don't match.

Aspects of the invention include monitoring frames of bits received at a receiver for transmission errors. At least one of the received frames of bits includes cyclic redundancy code (CRC) bits for a first type of CRC check. It is determined whether a change in transmission errors has occurred in the received frames by performing the first type of CRC check based at least in part on the received CRC bits and payload bits in the received frames. A change from the first type of CRC check to a second type of CRC check is initiated at the receiver based at least in part on determining that a change in transmission errors has occurred. The change is synchronized between the receiver and the transmitter, and performed in parallel with functional operations performed by the receiver.

Aspects of the invention include receiving a specified number of frames of bits at a receiver. At least one of the received frames includes cyclic redundancy code (CRC) bits. The specified number of frames is based at least in part on a CRC rate. It is determined, by performing a CRC check on the received frames, whether a change in transmission errors has occurred in the received frames. An increase in the CRC rate is initiated at the receiver based at least in part on determining that a change in transmission errors has occurred in the received frames. The increase in the CRC rate is synchronized between the receiver and the transmitter; and performed in parallel with functional operations performed by the receiver.