H04L1/205

Systems and methods for reducing redundant jitter cleaners in wireless distribution systems

A digital routing unit (DRU) within a wireless distribution system (WDS) couples to multiple signal sources (e.g., base band units (BBU)) through common public radio interface (CPRI) links in such a fashion that clock reconditioning circuitry within the DRU is consolidated. That is, instead of each receiver circuit at each input at the DRU having its own clock reconditioning circuit, signals from the same network operator may be multiplexed so as to select a single signal and, from that single signal, recover a cleaned clock signal for use by all the receivers that receive signals from that network operator.

Methods and apparatus for determining a number of connections to use at a given time and/or the level of error correcting coding to use based on connection scores
10856348 · 2020-12-01 · ·

A first communications device may use one or a plurality of communications connections in parallel for a communications session between the first communications device and the second communications device. The first device makes decisions as to the number of connections to use, the level of error correcting code to use, and/or the level of packet redundancy to use based on test scores corresponding to one or more communications session connections. The first communications device generates a first test score corresponding to a first communications session connection based on a test performed over a first test path between the first communications device and a test server, said first communications session connection and the first test path sharing a common link, e.g., a common wireless link between the first device and an access point. The first device may generate and use an overall connection score corresponding to a plurality of session connections.

Jitter buffer apparatus and method

Disclosed is an apparatus and method operative to receive packets of media from a network including a receiver unit operative to receive the packets from the network, a jitter buffer data structure for receiving the packets in an ordered queue, the jitter buffer data structure having a tail into which the packets are input; a plurality of heads defining points in the jitter buffer data structure from which the ordered queue of packets are to be played back, the heads comprise an adjustable actual playback head coupled to an actual playback unit and at least one prototype head, each prototype head having associated therewith a target latency a processor having decision logic operable to determine a cost of achieving the associated target latency for each prototype head, wherein the decision logic compares the costs determined for each prototype head to identify a particular target latency and head location for the actual playback head of the buffer and a playback unit coupled to the processor for actual playback of the playback head of the buffer, such that the particular target latency of the jitter buffer data structure is determined at playback of the buffer rather than upon input of the packets into the jitter buffer data structure.

RADIO RESOURCE CONFIGURATION METHOD, BASE STATION AND USER EQUIPMENT
20200314862 · 2020-10-01 · ·

A radio resource configuration method, a base station and a UE are provided. The radio resource configuration method includes: acquiring an arrival time of each data packet; acquiring a delivery time or a reception time of each data packet; calculating an average delay of downlink data packets within a time period or a proportion of uplink data packets whose reordering delay at a PDCP layer within a time period is greater than or smaller than a predetermined delay threshold, the average delay of the downlink data packets including one or more of average delays of the downlink data packets for a same UE, of a same bearer type, through a same transmission path, on a same RB and in a same QoS flow within the time period; and performing radio resource configuration based on the calculated average delay or the calculated proportion.

Method for determining phase noise in a periodically modulated signal

A method for determining phase noise in a periodically modulated signal is described. The modulated signal is processed to generate a processed signal from the modulated signal. At least an approximate period of a modulation of the modulated signal is determined from the processed signal. The type of modulation of the modulated signal is determined from the processed signal. The modulated signal is demodulated based on the determined period and the determined type of modulation to generate a demodulated signal, and the phase noise is determined from the demodulated signal. Moreover, a measurement device is described.

Waveform observation system and method for waveform observation

A waveform observation system includes two communication nodes, a waveform observation apparatus, and a signal generation portion. The two communication nodes execute a full-duplex communication by a differential signal through a transmission line. The waveform observation apparatus observes a communication signal waveform in the transmission line in response to an input of a trigger signal. The signal generation portion outputs the trigger signal. One of the two communication nodes generates a clock signal, and transmits a signal in synchronization with the clock signal. Remaining one of the two communication nodes reproduces the clock signal included in the signal received from the one of the two communication nodes, and transmits a signal in synchronization with the clock signal that is reproduced. The signal generation portion outputs the trigger signal when equal to or more than two symbols indicated by the signal output to the transmission line consecutively coincide with one another.

Setting device, setting method, recording medium to which setting program is recorded, communication system, client device, and server device
10749781 · 2020-08-18 · ·

Provided is a setting device and the like with which correct estimation of a communication band is possible. The setting device 101 has a transmission unit 102 that, on the basis of a first timing at which a first information processing device 401 transmits to a second information processing device 402 a first signal for measuring a communication band which pertains to a communication network 403, transmits to the second information processing device 402 a setting signal for setting a communication unit 407 of the second information processing device 402 to a communication-enabled state.

ADC-based SerDes with sub-sampled ADC for eye monitoring

Digital serializer/deserializer circuitry includes a data path and a date eye monitoring path. The data path includes a first analog-to-digital converter (ADC) to sample incoming data at a first rate, first digital filter circuitry to filter output of the first ADC, and a data slicer coupled to output of the first digital filter circuitry to output data above a threshold. The monitoring path includes a second ADC to sample the incoming data at a second rate lower than the first rate and to take samples at varying points along the incoming data waveform, second digital filter circuitry to filter output of the second ADC, and another data slicer coupled to output of the second digital filter circuitry to output data above an adjustable threshold and to sweep through varying threshold values. Error rate circuitry compares outputs of the data slicers to determine a data eye error rate.

Reducing end-to-end delay for audio communication

An apparatus includes de-jitter buffer control circuitry configured to determine an arrival delay value, to determine a receive time of a first audio packet of a talk spurt, to determine a target delay value associated with a de-jitter buffer based on the arrival delay value and the receive time of the first audio packet. The apparatus also includes a decoder timing control circuitry configured, in response to detecting the first audio being dequeued from the de-jitter buffer, to cause a decoder to start decoding of the first audio packet.

Eye diagram measurement device and eye diagram measurement method

An eye diagram measurement device includes a first mapping circuitry, a count circuitry, a second mapping circuitry and a memory circuitry. The first mapping circuitry maps one of plurality of internal signals of an electronic device to a first data signal having a predetermined number of bits. The counter circuitry performs a counting operation according to the first data signal and a plurality of signal values associated with the predetermined number of bits, to generate a plurality of count signals. The second mapping circuitry maps the count signals respectively to a plurality of eye diagram measurement signals corresponding to a present phase. The memory circuitry stores the eye diagram measurement signals in order to provide the eye diagram measurement signals to an external system for generating an eye diagram measurement result of the electronic device.