Embodiments include apparatuses, methods, and systems for jitter equalization and phase error detection. In embodiments, a communication circuit may include a data path to pass a data signal and a clock path to pass a clock signal. A jitter equalizer may be coupled with the data path and/or clock path to provide a programmable delay to the data signal and/or clock signal, respectively. The delay may be determined by a training process in which a supply voltage may be modulated by a modulation frequency. The delay may be dependent on a value of the supply voltage, such as a voltage level and/or jitter frequency component of the supply voltage. A phase error detector is also described that may be used with the communication circuit and/or other embodiments.

Embodiments are disclosed for computing an eye diagram based on input pulse responses. An example method includes receiving a set of input pulse responses in one or more unit interval (UI) spaced samples. The set of input pulse responses is generated based on measuring a signal histogram of a receiver of a pulse amplitude modulation analog signal. The method further includes receiving a set of voltage range constraints and generating a matrix based at least in part on an element-wise trigonometric-based operation performed on one or more products of each element of the set of input pulse responses and the set of voltage range constraints. The method further includes generating an eye diagram probability density function based on the matrix and computing an eye diagram based on the eye diagram probability density function, the voltage range constraints, and time data associated with the one or more unit interval spaced samples.

A method can include receiving an input signal having multiple signal edges, performing an initial scan of the input signal to identify peaks corresponding to the signal edges, and determining whether each peak is a Uniformly Synchronous (US) edge or a Quasi-Synchronous (QS) edge. The method can also include generating a final waveform and displaying the final waveform on a display device.

An information terminal sequentially transmits one or more packets to an information distribution server, receives acknowledgments for the transmitted packets from the information distribution server, and records a round trip time and occurrence of packet loss for each of the transmitted packets. Among one or more packet sequences, the information terminal counts the number of packet sequences which are such that the number of packet losses included in each of the packet sequences and an increase state of the round trip time for packets included in the packet sequence satisfy respective predetermined conditions. Each of the one or more packet sequences has multiple continuous packets including one or more packets, for which packet loss is recorded among the transmitted packets, at the top. The information terminal calculates a packet loss ratio on the basis of the counted number and the number of transmitted packets.

The invention provides a semiconductor device capable of diagnosing communication network quality. Disclosed is a semiconductor device that is coupled to a light source, the semiconductor device including a signal processing unit that is coupled to an interface module and transmits and receives a command signal to increase or decrease illumination intensity of the light source and a deterioration detector that detects deterioration of the interface module, based on whether or not change timing of a signal representing data of a command signal received by the interface module falls within a predetermined interval.

A scheme for noise floor de-embedding by identifying a link or relationship between noise floor from an oscilloscope and phase jitter impact on a toggling signal. The scheme uses phase or electrical spectrum and phase detection for noise floor recognition. The scheme de-embeds the impact from random noise and also removes deterministic noise or jitter from the oscilloscope. The scheme provides accurate jitter analysis for a circuit (e.g., clock data recovery circuit) after de-embedding noise floor for the oscilloscope

A video encoding device (e.g., a wireless transmit/receive unit (WTRU)) may transmit an encoded frame with a frame sequence number using a transmission protocol. The video encoding device, an application on the video encoding device, and/or a protocol layer on the encoding device may detect a packet loss by receiving an error notification. The packet loss may be detected at the MAC layer. The packet loss may be signaled using spoofed packets, such as a spoofed NAM packet, a spoofed XR packet, or a spoofed ACK packet. A lost packet may be retransmitted at the MAC layer (e.g., by the encoding device or another device on the wireless path). Packet loss detection may be performed in uplink operations and/or downlink operations, and/or may be performed in video gaining applications via the cloud. The video encoding device may generate and send a second encoded frame based on the error notification.

A method for transmitting multimedia according to the present disclosure comprises: a step of transmitting a first message including fixed delay information and buffer information with respect to a receiving device; and a step of transmitting a packet relating to the multimedia and including a transmission time stamp, wherein a first packet is sent out from a digital buffer of the receiving device at a time determined by adding up the transmission time stamp and the fixed delay information.

A device includes a transmitter coupled to a node, where the node is to couple to a wired link. The transmitter has a plurality of modes of operation including a calibration mode in which a range of communication data rates over the wired link is determined in accordance with a voltage margin corresponding to the wired link at a predetermined error rate. The range of communication data rates includes a maximum data rate, which can be a non-integer multiple of an initial data rate.

A receiver includes a feed-forward equalizer, a first detector, a jitter estimation circuit, and a jitter mitigation circuit. The feed-forward equalizer is configured to equalize channel gain of digitized samples of a received signal and to output equalized samples. The first detector is configured to detect symbols in the equalized samples. The jitter estimation circuit is configured to estimate jitter in the equalized samples by estimating a deviation in periodicity between pairs of the equalized samples. The jitter mitigation circuit comprises a linearized FIR filter configured to receive an input including the equalized samples or the detected symbols and to compensate inter symbol interference in the equalized samples due to the jitter as a function of the estimated jitter and an estimate of the inter symbol interference.