A signal generator includes inverse characteristic calculation means for calculating an inverse characteristic of a transfer function from an inverse characteristic of a frequency characteristic of a signal based on the transmission standard, inverse Fourier transform means for calculating impulse responses of a plurality of points by performing inverse Fourier transform on the inverse characteristic of the transfer function, impulse response cutout means for cutting out the points for a predetermined number of taps from the impulse response, frequency characteristic calculation means for calculating a frequency characteristic based on values of the points for the number of taps cut out from the impulse response, and display control means for displaying on a display screen, the frequency characteristic calculated by the frequency characteristic calculation means and an ideal frequency characteristic read from an S parameter file of a device under test.

The present invention is directed to data communication systems and techniques thereof. More specifically, embodiments of the present invention provide a retimer module that includes plurality of communication lanes for interfacing with a host system and a line system. The retimer module includes a link monitor and cross point sections. The retimer also includes a management interface module. There are other embodiments as well.

A signal generator includes inverse characteristic calculation means for calculating an inverse characteristic of a transfer function from an inverse characteristic of a frequency characteristic of a signal based on the transmission standard, inverse Fourier transform means for calculating impulse responses of a plurality of points by performing inverse Fourier transform on the inverse characteristic of the transfer function, impulse response cutout means for cutting out the points for a predetermined number of taps from the impulse response, frequency characteristic calculation means for calculating a frequency characteristic based on values of the points for the number of taps cut out from the impulse response, and display control means for displaying on a display screen, the frequency characteristic calculated by the frequency characteristic calculation means and an ideal frequency characteristic read from an S parameter file of a device under test.

A UART includes a transmission register, a receive register, a virtual remappable pin, a parity error check circuit to evaluate contents of the receive register for a parity error, and control logic to determine contents of the transmission register. The contents include underlying data and a parity bit based thereupon. The control logic is to route the contents through the first virtual remappable pin to the receive register. The control logic is to, before reception of the entire contents at the receive register, cause modified contents to be provided to the receive register. The modified contents are to cause a parity error. The modified contents are to include different underlying data or a different parity bit than the contents of the transmission register. The control logic is to determine whether the parity error check circuit detected the parity error.

Described are methods and circuits for margin testing digital receivers. These methods and circuits prevent margins from collapsing in response to erroneously received data and can thus be used in receivers that employ historical data to reduce intersymbol interference (ISI). Some embodiments detect receive errors for input data streams of unknown patterns and can thus be used for in-system margin testing. Such systems can be adapted to dynamically alter system parameters during device operation to maintain adequate margins despite fluctuations in the system noise environment due to e.g. temperature and supply-voltage changes. Also described are methods of plotting and interpreting filtered and unfiltered error data generated by the disclosed methods and circuits. Some embodiments filter error data to facilitate pattern-specific margin testing.

An integrated circuit is operable in two modes, including a test mode in which a pattern of variation is injected into a receiver's sampling clock and used to simulate jitter. Adding frequency offset, jitter or both, to this clock can be equivalent to adding jitter of an equal magnitude but opposite sign in a transmitted test signal. In this way, a clock can be produced that simulates timing variations that can be encountered during mission function operation of the device under test, while test input data is applied by local pattern generators or other data sources that, under test conditions, do not, or need not, exhibit such variations. In detailed embodiments, these techniques can be separately employed in one or more clock and data recovery circuits (CDRs) of the integrated circuit; for example, a first local clock recovery circuit in a first receiver can be caused to produce a test clock which simulates a condition to be tested, and while a second receiver in the plurality of receivers that includes a second local clock recovery circuit is caused to use the test clock in place of the reference clock while receiving a test data sequence at its input.

Described are methods and circuits for margin testing digital receivers. These methods and circuits prevent margins from collapsing in response to erroneously received data, and can thus be used in receivers that employ historical data to reduce intersymbol interference (ISI). Some embodiments detect receive errors for input data streams of unknown patterns, and can thus be used for in-system margin testing. Such systems can be adapted to dynamically alter system parameters during device operation to maintain adequate margins despite fluctuations in the system noise environment due to e.g. temperature and supply-voltage changes. Also described are methods of plotting and interpreting filtered and unfiltered error data generated by the disclosed methods and circuits. Some embodiments filter error data to facilitate pattern-specific margin testing.

A method for testing a vehicle-to-X communication module by means of a diagnostic device as well as an associated vehicle-to-X communication module and an associated diagnostic device. During a test mode messages are exchanged between the vehicle-to-X communication module and the diagnostic device, and evaluated in order to detect errors.

An operation unit 2 sets a Flit length according to the number of lanes, a mask pattern length and a mask pattern period for masking a portion corresponding to an SKP OS, and a threshold value for Flit error determination. In an error detector 4, a symbol mask generation unit 25 generates a mask pattern, an error detection unit 28 detects and counts an error in the portion corresponding to Flit by dividing the mask pattern at intervals of a Flit length of a PAM4 signal from a device under test, and masking a portion corresponding to the SKP OS with the mask pattern, and a Flit error detection unit 29 detects and counts an FEC symbol error in the portion corresponding to Flit for each ECC group, and determines the ECC group in which the number of FEC symbol errors exceeds a threshold value to be a Flit error.

A parameter adjustment method and apparatus are provided. The parameter adjustment method for a communication device with a SerDes link includes: acquiring, by the communication device, a current ambient temperature of the communication device; and if according to a preset correspondence between a temperature range and a parameter, the current ambient temperature is determined to be not corresponding to a SerDes parameter of the communication device, adjusting the SerDes parameter of the communication device according to the correspondence. The SerDes parameter of the communication device is adjusted in real time, thereby improving reliability of a SerDes link of the communication device, and reducing a bit error rate of the SerDes link.