A redriver is provided that includes a receiver to receive a signal from a first device that includes a portion of a defined binary sequence, a drift buffer to retime the binary sequence and provide a seed to a linear feedback shift register (LFSR) from the binary sequence, the LFSR to generate an expected version of the binary sequence from the seed, and pattern checking logic to compare a sequence in subsequent signals received from the first device with the expected version of the binary sequence generated by the LFSR.

Described are methods and circuits for margin testing digital receivers. These methods and circuits prevent margins from collapsing in response to erroneously received data, and can thus be used in receivers that employ historical data to reduce intersymbol interference (ISI). Some embodiments detect receive errors for input data streams of unknown patterns, and can thus be used for in-system margin testing. Such systems can be adapted to dynamically alter system parameters during device operation to maintain adequate margins despite fluctuations in the system noise environment due to e.g. temperature and supply-voltage changes. Also described are methods of plotting and interpreting filtered and unfiltered error data generated by the disclosed methods and circuits. Some embodiments filter error data to facilitate pattern-specific margin testing.

An integrated circuit includes a plurality of receivers, each having a clock and data recovery circuit. A first local clock recovery circuit in a first receiver can be caused to produce a test clock which simulates a condition to be tested, and while a second receiver in the plurality of receivers that includes a second local clock recovery circuit is caused to use the test clock in place of the reference clock while receiving a test data sequence at its input. The clock and data recovery circuits in the receivers can include clock control loops responsive to loop control signals to modify the selected reference clock to generate the local clock in response to selective one of (i) a corresponding data signal for normal operation or during a test, and (ii) a test signal applied to the clock control loop in which case the test clock is produced.

An operation unit 2 sets a Flit length according to the number of lanes, a mask pattern length and a mask pattern period for masking a portion corresponding to an SKP OS, and a threshold value for Flit error determination. In an error detector 4, a symbol mask generation unit 25 generates a mask pattern, an error detection unit 28 detects and counts an error in the portion corresponding to Flit by dividing the mask pattern at intervals of a Flit length of a PAM4 signal from a device under test, and masking a portion corresponding to the SKP OS with the mask pattern, and a Flit error detection unit 29 detects and counts an FEC symbol error in the portion corresponding to Flit for each ECC group, and determines the ECC group in which the number of FEC symbol errors exceeds a threshold value to be a Flit error.

An abnormality detection device includes processing circuitry configured to input a normal packet to a Bidirectional Encoder Representations from Transformers (BERT) model learned using the normal packet, and acquire a size of Attention for each byte portion when encoding of the normal packet is performed, sample an important byte portion of the normal packet based on the size of the Attention of each byte portion of the normal packet acquired, and rewrite the sampled important byte portion to a random byte to generate a pseudo-abnormal packet, and determine a threshold value of an abnormality degree for detecting an abnormal packet based on the abnormality degree of the generated pseudo-abnormal packet group and normal packet group.

Devices, networks, systems, methods, and processes for determining receiver performance metric of a network device are described herein. A device may utilize one or more error patterns associated with the network device to retrieve one or more symbol errors from the one or more error patterns. The device can determine an error threshold for a segment based on a predefined Bit Error Rate (BER) level for the segment. The device may generate a performance metric for the segment based on the error threshold and the retrieved symbol errors. The device can generate a receiver performance metric based on performance metrics of segments. The device may determine a Code Error Ratio (CER) and can predict a Frame Loss ratio (FLR) associated with the network device based on the CER.