A receiver includes a circuit designed to process, based on a plurality of timed waveform reference locations, a waveform signal, the waveform signal comprising a message. The circuit may include a clock source, an input configured to receive the waveform signal, a time location reference circuit coupled to the clock source, the time location reference circuit designed to output the plurality of timed waveform reference locations, each timed waveform reference location being set by the clock, and a signal processing circuit coupled to the time location reference circuit, the signal processing circuit designed to generate an output voltage in a response to the waveform signal being inputted into the signal processing circuit through the input and processed at each timed waveform reference location from the series of timed waveform reference locations. A transmitter that generates the waveform signal can be also provided where the clocks are matched.

Some embodiments include an apparatus, method, and computer program product for high precision device synchronization of electronic devices in a shared medium. Some embodiments include a first electronic device that utilizes a combination of synchronization techniques to synchronize with a second electronic device. The first electronic device receives a first signal from the second electronic device that includes network-based synchronization data and marker data, and performs network-based synchronization with the second electronic device at a first synchronization accuracy. The first electronic device receives a second signal, and uses the marker data and phase lock synchronization to detect a frequency change of the second signal received, as well as to determine a corresponding time marker. The first electronic device updates a clock of the first electronic device based at least on the corresponding time marker, the network-based synchronization data, and the marker data.

The present disclosure relates to a bidirectional communication circuit for bidirectional communication between a first differential wired network and a second differential wired network and a related method of operating the bidirectional communication circuit. In particular, the present disclosure relates to a bidirectional communication circuit designed to prevent timing glitches and simultaneous transmission of data from the first network to the second network and from the second network to the first network.

Techniques are disclosed relating to time synchronization in a network. In some embodiments, an apparatus includes a first circuit having a first clock configured to maintain a local time value for a node coupled to a network. The first circuit is configured to send a first message to a second circuit. The first message includes a first nonce. The second circuit has a second clock that maintains a reference time value for the network. The first circuit receives a second message from the second circuit, the second message including a second nonce and is associated with a timestamp identifying the reference time value. The first circuit compares the first nonce to the second nonce to determine whether the timestamp is valid and, in response to determining that the timestamp is valid, uses the timestamp to synchronize the first clock with the second clock.

According to one embodiment, an interface system includes a receiver, a first clock generator, a second clock generator, and a sampling circuit. The receiver is configured to receive a first clock and serial data from a host. The first clock generator includes a first voltage controlled oscillator (VCO) and is configured to generate a second clock on the basis of the first clock. The second clock generator includes a second voltage controlled oscillator (VCO) and is configured to generate a third clock on the basis of the serial data. The sampling circuit is configured to sample reception data on the basis of the third clock and the serial data.

Methods and systems are described for sequentially obtaining a plurality of data streams, the plurality of data streams comprising a data stream in a current condition, a data stream in a skewed-forward condition, and a data stream in a skewed-backward condition, calculating, for each data stream in the plurality of data streams, a corresponding set of cost-function values by obtaining a corresponding set of eye measurements, the eye measurements obtained by adjusting a sampling threshold of a sampler generating a plurality of samples of the data stream, the plurality of samples comprising edge samples and data samples, wherein the data stream is sampled at a rate equal to twice a rate of the data stream and calculating the corresponding set of cost-function values based on the corresponding set of eye measurements, and generating a skew control signal based on a comparison of the sets of calculated cost-function values.

The invention concerns a circuit for transferring a data from one clock domain to another clock domain, the circuit comprising: a digital circuit configured to generate a data signal synchronized with a source clock signal, and to receive such data by sampling the data signal synchronized with a target clock signal; a phase comparator which is configured to determine a phase relationship between the source clock signal and the target clock signal; and a data signal synchronization circuit configured to receive data signal transitions that are synchronized with the source clock signal, and to provide a synchronized data signal transitions of which are synchronized with the target clock signal.

An electronic circuit for converting a signal between digital and analog in a burst mode, including a processor configured to utilize a synchronizing clock signal, a converter configured to convert a signal data between digital and analog using a converter clock signal, a phase comparator configured to determine a phase relationship between the synchronizing clock signal and the converter clock signal, and a digital signal processor coupled to the phase comparator and configured to receive an information about the phase relationship, wherein the digital signal processor is configured to apply a delay to the signal data being exchanged between the processor and. The synchronizing clock signal and the converter clock signal have a predetermined frequency relationship.

An integrated access system, a configuration method, and a baseband unit are provided. An embodiment of this application provides an integrated access system, including a first baseband unit BBU, a second BBU, a first data exchange unit, a first base station network management subsystem, a second base station network management subsystem, and a first pico remote radio unit pRRU. The first BBU is connected to the first data exchange unit, the first BBU is connected to the first base station network management subsystem, the first BBU is connected to the second BBU, the second BBU is connected to the second base station network management subsystem, and the first pRRU is connected to the first data exchange unit.

A system is provided for generating a time reference in duty-cycled wireless communications. The system includes at least one master module including a master transceiver adapted to transmit data packets. The system further includes at least one slave module including a slave transceiver adapted to receive the data packets. The slave module further includes a signal generator adapted to generate a clock signal with a period equal to the time interval of two data packets transmitted by the master module. Moreover, the slave module further includes a slave timer adapted to utilize the clock signal as a time reference in order to perform the sleep/wakeup control for the slave module.