Patent classifications
H04L7/0012
Method and apparatus for synchronous signaling between link partners in a high-speed interconnect
Loop timing is performed in a Reconciliation Sublayer (RS) so that the transmit clock frequency can be adjusted to be equal to the receive clock frequency for the entire PHY (including the physical coding sublayer (PCS)). One of two partners is selected to be the timing Slave to the other. If only one partner is capable of loop timing, that partner becomes the Slave. If both partners are capable of loop timing, symmetry breaking can be used to determine which partner should become Slave.
TIMING DETECTION AND CORRECTION METHOD FOR A SLAVE DEVICE IN AN IO-LINK COMMUNICATION AND SLAVE DEVICE OF AN IO-LINK COMMUNICATION
A slave device for IO-Link communication with a master device, wherein the master device and the slave device operate on a common basic timing, the slave device including at least one Universal Asynchronous Receiver Transmitter (UART) module configured to detect an INIT request sent from the master device during communication setup, calculate an actual timing of the master device from the INIT request and correct an initial timing of the slave device to an actual timing of the slave device based on the actual timing of the master device.
System for establishing and maintaining a clock reference indicating one-way latency in a data network
A method for indicating one-way latency in a data network, with continuous clock synchronization, between first and second node having clocks that are not synchronized with each other includes a continuous synchronization session and a measurement session. The method repetitively sends predetermined synchronization messages from the first node to the second node and from the second node to the first node, calculates a round trip time for each message at the first node, updates a synchronization point if the calculated round trip time is smaller than a previously calculated round trip time, stores the updated synchronization points of a synchronization window, and calculates a virtual clock from the updated synchronization points of the synchronization window. The measurement session collects multiple measurements of one-way latency between the first and second nodes using the virtual clock, and generates a latency profile by interpolating the multiple measurements.
Integrated access system, configuration method, and baseband unit
Example integrated access systems, configuration methods, and baseband units are described. One example integrated access system includes a first baseband unit (BBU), a second BBU, a first data exchange unit, a first base station network management subsystem, a second base station network management subsystem, and a first pico remote radio unit (pRRU). The first BBU is connected to the first data exchange unit, the first BBU is connected to the first base station network management subsystem, the first BBU is connected to the second BBU, the second BBU is connected to the second base station network management subsystem, and the first pRRU is connected to the first data exchange unit.
Hardware Clock with Built-In Accuracy Check
A network device includes one or more ports for connecting to a communication network, packet processing circuitry and clock circuitry. The packet processing circuitry is configured to communicate packets over the communication network via the ports. The clock circuitry includes a hardware clock configured to indicate a network time used for synchronizing network devices in the communication network, and a built-in accuracy test circuit configured to check an accuracy of the hardware clock.
Receiver for high precision synchronization in a shared medium
Some embodiments include an apparatus, method, and computer program product for high precision device synchronization of electronic devices in a shared medium. Some embodiments include a first electronic device that utilizes a combination of synchronization techniques to synchronize with a second electronic device. The first electronic device receives a first signal from the second electronic device that includes network-based synchronization data and marker data, and performs network-based synchronization with the second electronic device at a first synchronization accuracy. The first electronic device receives a second signal, and uses the marker data and phase lock synchronization to detect a frequency change of the second signal received, as well as to determine a corresponding time marker. The first electronic device updates a clock of the first electronic device based at least on the corresponding time marker, the network-based synchronization data, and the marker data.
Method for synchronizing networks
A method for synchronizing networks is disclosed. A first wired communication system having a first time base is set up in a first network. A second wired communication system having a second time base is set up in a second network. The first network and the second network are connected to a wireless communication system via a first translation unit and a second translation unit, respectively. The first translation unit and the second translation unit are synchronized to one another according to a third time base of the wireless communication system independently of the first time base and the second time base. A third synchronization message is transmitted from the first translation unit to the second translation unit. A transmission time for the third synchronization message in the third time base is determined and is used to synchronize the second time base to the first time base.
INTEGRATED CIRCUIT AND OPERATING METHOD THEREOF
Provided is an integrated circuit. The integrated circuit includes a plurality of clock generators configured to respectively generate a plurality of clock signals, a plurality of logic circuits configured to operate in synchronization with the plurality of clock signals, and controller circuitry configured to identify meta-stability information based on frequencies of the plurality of clock signals, and configured to control at least one clock generator so that at least one of the plurality of clock signals is randomly delayed in response to the meta-stability information.
Lead-on detection circuitry of biopotential acquisition system
The present invention provides a lead-on detection circuitry of a biopotential acquisition system. The lead-on detection circuitry includes an input terminal, a duty-cycle controller, a transmitting signal generator and a mixer-based receiver. The duty-cycle controller is configured to generate a first clock signal. The transmitting signal generator is configured to generate a transmitting signal to the input terminal according to the first clock signal. The mixer-based receiver is configured to perform a mixing operation based on the first clock signal and the transmitting signal to generate an output signal, wherein the output signal indicates if an electrode of the biopotential acquisition system is in contact with a human body, and the electrode is coupled to the input terminal.
Synchronized multi-channel communication device and method
An apparatus and method to transmit and receive messages within and near the noise floor by pulsed signals that are time synchronized and are not easily intercepted by use of frequency and time slots as well as intermittent transmissions.