A controller includes circuitry configured to: synchronize a master clock with an external global clock and set a master time based on the master clock; synchronize a controller clock with the master clock and perform time synchronization to synchronize a controller time based on the controller clock with the master time; transmit controller time data indicating the synchronized controller time to at least one local device; set a plurality of time windows corresponding to a plurality of clock cycles of a clock signal for the time synchronization; determine whether one clock cycle of the plurality of clock cycles has started within one time window of the plurality of time windows, the one time window corresponding to the one clock cycle; and suspend the time synchronization corresponding to the one clock cycle, in response to determining that the one clock cycle has not started within the one time window.

A system includes a processor and a memory. The memory stores instructions executable by the processor to receive first and second media units with respective first and second time stamps that are assigned based on a first clock cycle time and a data transmission rate, and to assign an adjusted time stamp to the second media unit based on the first clock cycle time, a second clock cycle time, the first time stamp, and the data transmission rate.

A time synchronization system includes a master and slave devices connected to each other via a data bus and a signal line dedicated to transmission of a fixed-period signal. The master device transmits the fixed-period signal through the signal line regularly at a transmission period, and transmits start time information indicating a transmission start time at which transmission of the fixed-period signal is started and transmission period information indicating the transmission period for the fixed-period signal through the data bus. The slave device counts a number of times the fixed-period signal is received and calculates, as a current time in the master device, a transmission time at which the master device transmits the fixed-period signal based on the number of times the fixed-period signal is received. The slave device corrects the time to the calculated current time in the master device.

A semiconductor device outputs, as an output signal synchronized to a phase-locked loop clock signal, a synchronized input signal that is synchronized to a reference clock signal of a phase-locked loop circuit. The semiconductor device includes the phase-locked loop circuit, a first flip-flop that receives the input signal in synchronization with the reference clock signal on the basis of a feedback signal inputted to a phase comparator of the phase-locked loop circuit 10, and a second flip-flop that receives an output from the first flip-flop on the basis of the phase-locked loop clock signal. The second flip-flop outputs the output from the first flip-flop as the output signal. A setup time to synchronize the input signal to the phase-locked loop clock signal is set to one half of a period of the reference clock signal.

A time transfer modem includes a radio frequency integrated circuit (RFIC), a radio frequency (RF) front end, and processing circuitry. The RF front end is configured to receive and up-convert an input for time transfer with a remote station to generate an up-converted timing signal centered at a select frequency that is outside of a frequency range of interest but within an operational frequency range of the RFIC. The RF front end may also be configured to attenuate, via a pre-selection filter, up-converted adjacent signals to generate a filtered timing signal at the select frequency. The RFIC may be configured to down-convert and digitize the filtered timing signal to generate a digitized timing signal for signal processing by the processing circuitry to determine a clock difference between a local clock signal and the digitized timing signal that originated from the remote station.

A time transfer modem includes a radio frequency integrated circuit (RFIC), a radio frequency (RF) front end, and processing circuitry. The RF front end is configured to receive and up-convert an input for time transfer with a remote station to generate an up-converted timing signal centered at a select frequency that is outside of a frequency range of interest but within an operational frequency range of the RFIC. The RF front end may also be configured to attenuate, via a pre-selection filter, up-converted adjacent signals to generate a filtered timing signal at the select frequency. The RFIC may be configured to down-convert and digitize the filtered timing signal to generate a digitized timing signal for signal processing by the processing circuitry to determine a clock difference between a local clock signal and the digitized timing signal that originated from the remote station.

The present disclosure relates to a bidirectional communication circuit for bidirectional communication between a first differential wired network and a second differential wired network and a related method of operating the bidirectional communication circuit. In particular, the present disclosure relates to a bidirectional communication circuit designed to prevent timing glitches and simultaneous transmission of data from the first network to the second network and from the second network to the first network.

A communication apparatus includes a plurality of clocks configured to output signals indicating current times, a plurality of counter units configured to synchronize with the plurality of clocks using the signals indicating the current times output from the plurality of clocks, an instruction unit configured to give an instruction to acquire count values of the plurality of counter units, an acquisition unit configured to acquire the count values of the plurality of counter units based on the instruction from the instruction unit, and a calculation unit configured to calculate a difference between the acquired count values.

A slave communication apparatus including a clock recovering section that recovers a clock signal from a transmission signal having a first signal value when the clock is a first level, a second signal value when the clock is a second level and data has a first data value, and a third signal value between the first and second signal values when the clock is the second level and the data has a second data value; and a data recovering section that recovers the data, wherein the data recovering section sets the data threshold value to be a first setting value between the second and third signal values in response to the recovered data having the second data value, and sets the data threshold value to be a second setting value between the first and third signal values in response to the recovered data having the first data value.

A method includes, at a first node: transmitting a first calibration signal at a first time-of-departure measured by the first node; and transmitting a second calibration signal at a second time-of-departure measured by the first node. The method also includes, at a second node: receiving the first calibration signal at a first time-of-arrival measured by the second node; and receiving the second calibration signal at a second time-of-arrival measured by the second node. The method further includes: defining a first calibration point and a second calibration point in a set of calibration points, each calibration point comprising a time-of-departure and a time-of-arrival of each calibration signal; calculating a regression on the set of calibration points; and calculating a frequency offset between the first node and the second node based on the first regression.