A multi-lane serializer device 1 includes serializer circuits 10.sub.1 to 10.sub.N and a controller 20. A phase difference detector of each serializer circuit detects a phase difference between a load signal and a first clock, and outputs an abnormal detection signal to the controller 20 when the detected phase difference is abnormal. When the controller 20 receives the abnormal detection signal from any of the serializer circuits, the controller 20 transmits a batch reset instruction signal to all the serializer circuits. Then, in all the serializer circuits, when a reset signal generator receives the batch reset instruction signal output from the controller 20, the reset signal generator transmits a reset instruction signal to a load signal generator to reset the operation of a load signal generation in the load signal generator.

The present invention provides a lead-on detection circuitry of a biopotential acquisition system. The lead-on detection circuitry includes an input terminal, a duty-cycle controller, a transmitting signal generator and a mixer-based receiver. The duty-cycle controller is configured to generate a first clock signal. The transmitting signal generator is configured to generate a transmitting signal to the input terminal according to the first clock signal. The mixer-based receiver is configured to perform a mixing operation based on the first clock signal and the transmitting signal to generate an output signal, wherein the output signal indicates if an electrode of the biopotential acquisition system is in contact with a human body, and the electrode is coupled to the input terminal.

Certain aspects of the present disclosure provide an apparatus for wireless communication. The apparatus generally includes a plurality of slave radio frequency (RF) devices, a master RF device configured to set a configuration parameter in a register to be applied by an RF slave device of the plurality of RF slave devices, and a clock line coupled between the master RF device and the plurality of slave RF devices. The slave RF device may be configured to: count a number of cycles of a clock signal on the clock line; and apply the configuration parameter for the slave RF device based on the count of the number of cycles, wherein the master RF device is further configured to disable an interrupt reporting function of the plurality of slave RF device during a time period between setting the configuration parameter in the register and the configuration parameter being applied.

A system for time synchronization of a network element including a GNSS receiver operative to receive at least one signal from at least one but less than four GNSS satellites, a locator operative to supply a location of a network element including the GNSS receiver to the GNSS receiver and a time synchronization calculator operative to time synchronize the network element with the GNSS satellites based on the at least one signal and the location.

Some embodiments include an apparatus, method, and computer program product for high precision device synchronization of electronic devices in a shared medium. Some embodiments include a first electronic device that utilizes a combination of synchronization techniques to synchronize with a second electronic device. The first electronic device receives a first signal from the second electronic device that includes network-based synchronization data and marker data, and performs network-based synchronization with the second electronic device at a first synchronization accuracy. The first electronic device receives a second signal, and uses the marker data and phase lock synchronization to detect a frequency change of the second signal received, as well as to determine a corresponding time marker. The first electronic device updates a clock of the first electronic device based at least on the corresponding time marker, the network-based synchronization data, and the marker data.

Systems and methods are disclosed herein for performing a time-triggered distribution of messages from a region of networked machines to multiple destinations. In an embodiment, the system runs a software-based synchronization process to synchronize each of a plurality of gateways with a reference clock, wherein each gateway is a machine on a perimeter of the region of networked machines and is connected to transmit messages to multiple destinations. The gateways receive messages from within the region of networked machines for distribution to multiple destinations outside the region of networked machines according to a distribution schedule based on absolute time relative to the reference clock. The gateways perform the distribution of received messages, wherein each gateway determines absolute time based on that gateway's synchronization with the reference clock.

An electronic device that coordinates a playback operation is described. In particular, an interface circuit in the electronic device may calculate, based on differences between transmit times when packets were transmitted by a second electronic device and receive times of the packets, relative drift as a function of time between a clock in the interface circuit and a second clock in the second electronic device. Then, the interface circuit may adjust, based on the relative drift, a clock circuit that provides the clock to eliminate the relative drift, and may determine a remaining time offset between the clock and the second clock. Next, the interface circuit may modify a future time when the second electronic device is to perform the playback operation based on the remaining time offset to determine a corrected future time, and may transmit information to the second electronic device specifying the corrected future time.

The present application discloses an asynchronous sampling architecture and a chip. The asynchronous sampling architecture is configured to receive a first input data string from the peer end, and the asynchronous sampling architecture includes: a first register, configured to buffer a first input data string, wherein the first input data string is written into the first register according to a peer end clock of the peer end; and a gated clock generation unit, configured to generate a gated clock, wherein the frequency of the gated clock is the same as the frequency of the peer end clock, and the first input data string is read out as a first output data string from the first register according to the gated clock.

A method at a first device for synchronising a first clock of the first device to a second clock of a second device, includes receiving a first message comprising an identifier from a third device; generating a first timestamp in dependence on the time at which the first message is received at the first device according to the first clock; receiving a second message from the second device comprising the identifier and a second timestamp, the second timestamp having been generated in dependence on the time at which the second device received the first message from the third device according to the second clock; and adjusting the first clock in dependence on a time difference between a time indicated by the first timestamp and a time indicated by the second timestamp.

A first device may provide, to a second device, a first message that includes a first request for a first type of precision time protocol (PTP) message and a second request for a second type of PTP message. The first device may receive, from the second device, a second message based on the first message. The second message may identify whether the first request and the second request are granted. The first device may provide, to the second device, a third message that instructs the second device to provide a first set of messages, associated with the first type of PTP message, and a second set of messages associated with the second type of PTP message. The first device may synchronize a first clock of the first device with a second clock of the second device based on the first set of messages and the second set of messages.