A receiver circuit includes a clock lane propagating a clock signal. A self-sampled clock applies a delayed version of the clock signal to the clock signal and compensation logic controls an amount of delay of the delayed version of the clock, based on a reference voltage offset (difference) between the receiver and a transmitter. The delayed version of the clock is centered on one unit interval of the clock. An offset correction is computed as a global offset value based on a clock duty cycle error, combined with a local offset value for each data lane, and is applied to data receiver front ends.

Systems and methods are disclosed herein for performing a time-triggered distribution of messages from a region of networked machines to multiple destinations. In an embodiment, the system runs a software-based synchronization process to synchronize each of a plurality of gateways with a reference clock, wherein each gateway is a machine on a perimeter of the region of networked machines and is connected to transmit messages to multiple destinations. The gateways receive messages from within the region of networked machines for distribution to multiple destinations outside the region of networked machines according to a distribution schedule based on absolute time relative to the reference clock. The gateways perform the distribution of received messages, wherein each gateway determines absolute time based on that gateway's synchronization with the reference clock.

A receiver circuit includes a clock lane propagating a clock signal. A self-sampled clock applies a delayed version of the clock signal to the clock signal and compensation logic controls an amount of delay of the delayed version of the clock, based on a reference voltage offset (difference) between the receiver and a transmitter. The delayed version of the clock is centered on one unit interval of the clock. An offset correction is computed as a global offset value based on a clock duty cycle error, combined with a local offset value for each data lane, and is applied to data receiver front ends.

An apparatus and method to transmit and receive messages within and near the noise floor by pulsed signals that are time synchronized and are not easily intercepted by use of frequency and time slots as well as intermittent transmissions.

In an example, a system includes circuitry on a first side of an isolation barrier and circuitry on a second side of the isolation barrier, where the isolation barrier is operable to electrically isolate the first side from the second side. The system also includes a trimmed oscillator, a first transmitter, and a first receiver on the first side, the trimmed oscillator coupled to the first transmitter. The system includes a tunable oscillator, a second transmitter, and a second receiver on the second side, the tunable oscillator coupled to the second receiver and the second transmitter. In the system, the first side is configured to transmit a training sequence to the second side, and the second side is configured to tune the tunable oscillator based on the training sequence.

A data synchronization method, device, equipment, system and storage medium. Including: if a first data packet received by a slave device from a master device during a current Bluetooth low energy (BLE) connection interval is a new data packet, the slave device generates a hardware synchronization signal, which is a synchronization signal generated by a pure hardware circuit; if a data synchronization time of the slave device with the master device is a preset time in the current BLE connection interval, then the slave device performs data synchronization with the master device at the data synchronization time through triggering by the hardware synchronization signal.

A method for synchronizing a first time domain with a second time domain of a system on chip includes a detection of at least one periodic trigger event generated in the first time domain, the second time domain or in a third time domain; acquisitions, made at the instants of the at least one trigger event, of the current timestamp values representative of the instantaneous states of the time domain(s) other than the trigger time domain; a comparison, made in the third time domain, between differential durations between current timestamp values which are respectively acquired successively; and a synchronization of the second time domain with the first time domain, on the basis of the comparison.

A method includes, at a first node: transmitting a first calibration signal at a first time-of-departure measured by the first node; and transmitting a second calibration signal at a second time-of-departure measured by the first node. The method also includes, at a second node: receiving the first calibration signal at a first time-of-arrival measured by the second node; and receiving the second calibration signal at a second time-of-arrival measured by the second node. The method further includes: defining a first calibration point and a second calibration point in a set of calibration points, each calibration point comprising a time-of-departure and a time-of-arrival of each calibration signal; calculating a regression on the set of calibration points; and calculating a frequency offset between the first node and the second node based on the first regression.

A system is provided for generating a time reference in duty-cycled wireless communications. The system includes at least one master module including a master transceiver adapted to transmit data packets. The system further includes at least one slave module including a slave transceiver adapted to receive the data packets. The slave module further includes a signal generator adapted to generate a clock signal with a period equal to the time interval of two data packets transmitted by the master module. Moreover, the slave module further includes a slave timer adapted to utilize the clock signal as a time reference in order to perform the sleep/wakeup control for the slave module.

A data handoff controller includes a counter coupled to supply a count value indicative of a skew between a first clock signal and a second clock signal. The first and second clock signal have a fundamental beat frequency. A greatest common factor circuit is used to determine the fundamental beat frequency and the second is reset based on the beat frequency. A sampling circuit samples first clock domain data with the second clock signal. The sampling circuit is controlled to sample, at least in part, based on the count value. The count value can be used to impose a blackout window in which data is not sampled to avoid sampling data around data transitions of the first clock domain data. The count value can also be used to select an edge of the second clock signal to use for sampling the first clock domain data to ensure first clock domain data is not sampled during data transitions.