A method having the steps of obtaining temporal information communicated to a first device; carrying out one or more of the following tests: a test to determine whether the first device is in a state following an initial operation, a battery replacement or other power outage, or a reset, a test to determine whether a deviation between temporal information of the clock and the communicated temporal information is less than or equal to a threshold which is specified, and a test to determine whether the communicated temporal information has the same date as the temporal information of the clock; and synchronizing the clock using the communicated temporal information if all of one or more defined conditions are satisfied, wherein one of the one or more conditions requires that at least one of the one or more tests carried out has a positive result.

A system includes a processor and a memory. The memory stores instructions executable by the processor to receive first and second media units with respective first and second time stamps that are assigned based on a first clock cycle time and a data transmission rate, and to assign an adjusted time stamp to the second media unit based on the first clock cycle time, a second clock cycle time, the first time stamp, and the data transmission rate.

This invention provides a secure method for sending data—private, arrival-time messaging. Private, arrival-time messaging is based on classical physics and not quantum mechanics. It insures a private language for communicators with privately-synchronized clocks. In this method, there is no encrypted message available to an eavesdropper. A private message is mapped onto a time measurement known only to an intended sender and an intended receiver such that a third party knowing only the arrival time of the message and not the time measurement can never know the private message.

A universal asynchronous receiver/transmitter (UART) module is disclosed. The UART module may include a receiver unit being clocked by a programmable receiver clock configured to sample an incoming data signal and comprising a counter clocked by said receiver clock, wherein the counter is reset to start counting with every falling edge of the data signal and to trigger a BRK detection signal if the counter reaches a programmable threshold value.

Methods and systems are described for receiving N phases of a local clock signal and M phases of a reference signal, wherein M is an integer greater than or equal to 1 and N is an integer greater than or equal to 2, generating a plurality of partial phase error signals, each partial phase error signal formed at least in part by comparing (i) a respective phase of the M phases of the reference signal to (ii) a respective phase of the N phases of the local clock signal, and generating a composite phase error signal by summing the plurality of partial phase error signals, and responsively adjusting a fixed phase of a local oscillator using the composite phase error signal.

An input signal is sampled at a current sampling phase by a sampler device of a receiver device. The sampled input signal is equalized by an adaptive equalizer of the receiver device. One or more parameters of the adaptive equalizer are adapted, based on the equalized input signal, under one or more adaptation constraints. Phase gradient information indicative of an offset of the current sampling phase from an optimal sampling phase is determined, and the one or more adaptation constraints of the adaptive equalizer are updated based on the phase gradient information to move the current sampling phase towards the optimal sampling phase.

Systems and methods are disclosed herein for performing a time-triggered distribution of messages from a region of networked machines to multiple destinations. In an embodiment, the system runs a software-based synchronization process to synchronize each of a plurality of gateways with a reference clock, wherein each gateway is a machine on a perimeter of the region of networked machines and is connected to transmit messages to multiple destinations. The gateways receive messages from within the region of networked machines for distribution to multiple destinations outside the region of networked machines according to a distribution schedule based on absolute time relative to the reference clock. The gateways perform the distribution of received messages, wherein each gateway determines absolute time based on that gateway's synchronization with the reference clock.

Methods and systems are described for receiving N phases of a local clock signal and M phases of a reference signal, wherein M is an integer greater than or equal to 1 and N is an integer greater than or equal to 2, generating a plurality of partial phase error signals, each partial phase error signal formed at least in part by comparing (i) a respective phase of the M phases of the reference signal to (ii) a respective phase of the N phases of the local clock signal, and generating a composite phase error signal by summing the plurality of partial phase error signals, and responsively adjusting a fixed phase of a local oscillator using the composite phase error signal.

A data transceiving system, comprising: a data receiving apparatus, comprising a data receiving side command pin and at least one data receiving side data pin; a data transmitting apparatus, comprising a data transmitting side command pin and at least one data transmitting side data pin. The data receiving apparatus transmits a first command signal from the data receiving side command pin to the data transmitting side command pin, and the data transmitting apparatus transmits a first response signal from the data transmitting side command pin to the data receiving side command pin. The data transmitting apparatus transmits data from the data transmitting side data pin to the data receiving side data pin. The data transmitting apparatus transmits a first data sampling clock signal from the data transmitting side command pin to the data receiving side command pin, to sample the data.

An LVDS data recovery method includes adopting three clocks to sample a received signal clock at the same time, wherein the first clock, the second clock and the third clock have the same frequency and different phases; determining whether the first clock is in the rising-falling edges of the received signal clock, in accordance with sampled levels of the received signal clock sampled by the three clocks at the same time; after determining the first clock is in the rising-falling edges of the received signal clock, adjusting phase of the first clock, and sampling the received data signal in accordance with adjusted phase of the first clock. The LVDS data recovery method ensures that the sampling clock edge is aligned with at the center of the data to be sampled. In case of high speed, the accuracy of the data sampling is guaranteed.