A communication apparatus includes a first counter configured to synchronize with a reference time, a second counter configured to synchronize with the first counter, a generation unit configured to generate a synchronization signal each time when a value of the second counter is incremented by a predetermined number, a correction unit configured to correct the value of the second counter toward a value of the first counter, and a control unit configured to control the correction unit to cause the correction unit to calculate a difference between the value of the first counter and the value of the second counter and, in a case where the calculated difference is greater than a predetermined threshold value, the correction unit to correct the value of the second counter step by step.

Methods and systems are described for receiving N phases of a local clock signal and M phases of a reference signal, wherein M is an integer greater than or equal to 1 and N is an integer greater than or equal to 2, generating a plurality of partial phase error signals, each partial phase error signal formed at least in part by comparing (i) a respective phase of the M phases of the reference signal to (ii) a respective phase of the N phases of the local clock signal, and generating a composite phase error signal by summing the plurality of partial phase error signals, and responsively adjusting a fixed phase of a local oscillator using the composite phase error signal.

The present technology proposes techniques for generating globally coherent timestamps. This technology may allow distributed systems to causally order transactions without incurring various types of communication delays inherent in explicit synchronization. By globally deploying a number of time masters that are based on various types of time references, the time masters may serve as primary time references. Through an interactive interface, the techniques may track, calculate and record data relative to each time master thus providing the distributed systems with causal timestamps.

A system includes a processor and a memory. The memory stores instructions executable by the processor to receive first and second media units with respective first and second time stamps that are assigned based on a first clock cycle time and a data transmission rate, and to assign an adjusted time stamp to the second media unit based on the first clock cycle time, a second clock cycle time, the first time stamp, and the data transmission rate.

A method for synchronizing baseband clocks in an OFDMA wireless microphone system is disclosed. An example method includes receiving a plurality of pilot subcarriers from an audio transmitter. The method also includes determining a timing offset estimate based on the pilot subcarriers. The method further includes determining a tuning value by passing the timing offset estimate through a proportional-integral controller. The method still further includes determining a modified reference signal by modifying a reference oscillator based on the tuning value. And the method yet further includes controlling (i) an audio sample clock and (ii) an antenna data clock based on the modified reference signal.

Provided are a method for time synchronization between a head-mounted device and a peripheral device. The method includes: obtaining sample data of an inertial measurement unit of the peripheral device, and determining a first timestamp representing a time at which the sample data is sampled; transmitting an interrupt request and the sample data to the head-mounted device, and determining a second timestamp representing a time at which the interrupt request is transmitted; determining a third timestamp representing a time at which the interrupt request is received by the head-mounted device; and determining a time difference based on the third timestamp and the second timestamp, and performing time compensation for the first timestamp based on the time difference to enable the peripheral device and the head-mounted device to complete the time synchronization with a unified time standard.

A multi-lane serializer device 1 includes serializer circuits 10.sub.1 to 10.sub.N and a controller 20. A phase difference detector of each serializer circuit detects a phase difference between a load signal and a first clock, and outputs an abnormal detection signal to the controller 20 when the detected phase difference is abnormal. When the controller 20 receives the abnormal detection signal from any of the serializer circuits, the controller 20 transmits a batch reset instruction signal to all the serializer circuits. Then, in all the serializer circuits, when a reset signal generator receives the batch reset instruction signal output from the controller 20, the reset signal generator transmits a reset instruction signal to a load signal generator to reset the operation of a load signal generation in the load signal generator.

A communication apparatus includes a first counter configured to synchronize with a reference time, a second counter configured to synchronize with the first counter, a generation unit configured to generate a synchronization signal each time when a value of the second counter is incremented by a predetermined number, a correction unit configured to correct the value of the second counter toward a value of the first counter, and a control unit configured to control the correction unit to cause the correction unit to calculate a difference between the value of the first counter and the value of the second counter and, in a case where the calculated difference is greater than a predetermined threshold value, the correction unit to correct the value of the second counter step by step.

An integrated circuit includes a first subsystem including a first clock generator configured to generate a first clock signal. The integrated circuit also includes a second subsystem including a second clock generator configured to generate a second clock signal. The first subsystem includes an edge detector configured to detect an edge of the second clock signal. The first clock generator generates the first clock signal with a selected phase relative to the second clock signal based on the edge of the second clock signal.

A semiconductor device outputs, as an output signal synchronized to a phase-locked loop clock signal, a synchronized input signal that is synchronized to a reference clock signal of a phase-locked loop circuit. The semiconductor device includes the phase-locked loop circuit, a first flip-flop that receives the input signal in synchronization with the reference clock signal on the basis of a feedback signal inputted to a phase comparator of the phase-locked loop circuit 10, and a second flip-flop that receives an output from the first flip-flop on the basis of the phase-locked loop clock signal. The second flip-flop outputs the output from the first flip-flop as the output signal. A setup time to synchronize the input signal to the phase-locked loop clock signal is set to one half of a period of the reference clock signal.