The present invention relates generally to integrated circuits. More particularly, the present invention provides a circuit and method for regulating a voltage for a high speed serializer/deserializer (SerDes) device. But it will be recognized that the technique can be used for regulating memory devices (e.g., DDR 4 SDRAM devices, DDR4 register devices, DDR4 controller devices), and other high speed data applications. In various embodiments, phase-interpolator is implemented in conjunction with a delay-lock loop (DLL) and an SR latch, where one or more outputs of the DLL is used by the SR latch. Additionally, such techniques can be used for a variety of applications such as network and/or computer storage systems, computer servers, hand held computing devices, portable computing devices, computer systems, network appliances and/or switches, routers, and gateways, and the like.

Techniques for pilot-aided carrier frequency and phase synchronization may use a three-pass process. In a first pass, initial frequency offset may be addressed, and a frame start time may be established. In a second pass, a fine frequency correction may be performed. In a third pass, phase variation may be tracked and corrected using a minimum set of pilot symbols.

Described herein are technologies related to an implementation of a digital-to-time converter (DTC) circuitry that utilizes a first interpolation and a second and finer interpolation to increase interpolation ranges. The DTC circuitry generates a fine-phase modulated signal generating at least two correlated signals, and generating coarse and fine interpolations of the correlated signals.

A communications system receiver is described providing automatic timing adjustment of receive data sampling. A concurrently received clock signal is used as both a reference for generation of internal receiver timing signals, and as an exemplar for adjustment of those timing signals to optimize received data sample timing.

An information processing apparatus is provided which includes a transmission unit for transmitting a query request for querying another device for a count value held by such other device, a reception unit for receiving a return of the count value from such other device, a correction unit for performing, at a predetermined period, correction processing for synchronizing sampling frequency with such other device based on the received count value, and a reproduction unit for reproducing content in synchronization with such other device based on the sampling frequency. The correction unit corrects by taking into account a Round Trip Time between the transmission of the query request and the reception of the return and residual difference occurred at a previous correction time.

A phase selector/phase interpolator circuit which includes two phase selector circuits and one phase interpolator circuit, each phase selector circuit includes N first tail current tubes, N phase selector units, a current source circuit and a comparison circuit. The current source circuit is selected as a load of the phase selector circuit. The comparison circuit compares a common-mode voltage of the two output clock signals output from the phase selector unit with a reference voltage, and performs negative feedback regulation on the first bias voltage of the first tail current tubes, so that the common-mode voltage can be controlled to be equal to the reference voltage, a tail current of the first tail current tubes is controlled to be equal to the current of the current source circuit, and the output waveform becomes a linear triangular wave.

Methods, systems, and apparatus, for enhanced clock frequency control. In some implementations, a clock system tracks time using a clock signal having a clock frequency. An interface receives a time reference from a reference clock, and a feedback loop synchronizes the clock system with the reference clock. The feedback loop includes a feedback loop controller configured to determine a clock frequency adjustment for the clock system based on an offset between the time reference and a time indicated by the clock system. The feedback loop also includes a smoothing filter configured to alter the clock frequency adjustment determined using the feedback loop controller. The feedback loop updates the clock frequency of the clock system based on the altered clock frequency adjustment.

The present disclosure discloses a two-point sampling optimized method and system for sinusoidal excitation-based frequency response measurement. A plurality of points are sampled at equal intervals within the starting frequency and ending frequency range as initial information, the interpolation error of each sub-frequency band is estimated according to existing sampling information, the sub-frequency band with the largest interpolation error is selected, two new sampling points are added within the sub-frequency band, and the above steps are repeated until the quantity of sampling points reaches the total quantity set by a user; and the user is asked whether new sampling points need to be added, if so, after the user specifies a new quantity of sampling points, the interpolation error of each sub-frequency band is estimated again and sampling continues, otherwise, the sampling ends. The present improves the practicality of a sinusoidal excitation-based frequency response measurement method.

A light communication system, receiver, and method for synchronizing a receiver with a transmitter so as to decode a data input stream transmitted by the transmitter and received at the receiver. The method includes: receiving a data input stream at a receiver, the data input stream having a first data rate that is set based on a transmitter clock rate; generating a wave; obtaining a phase error between the data input stream and the generated wave; determining a synchronized clock rate by using the phase error to adjust the frequency of the generated wave so as to match the frequency of the generated wave to the transmitter clock rate of the data input stream; and using the synchronized clock rate to decode the data input stream so as to obtain data encoded in the data input stream.