A display device including: a timing controller outputting a reference dock signal and a data packet, wherein the data packet includes a dock signal embedded in a data signal; a dock and data recovery (CDR) circuit receiving the reference clock signal and the data packet; and a display panel displaying an image based on the data packet, wherein, when the CDR circuit receives the reference clock signal, a frequency band of the reference clock signal is detected using a first internal clock signal, a parameter associated with jitter characteristics of the clock and data recovery circuit is adjusted according to the detected frequency band, and a second internal clock signal is output by adjusting a frequency of the first internal clock signal, and when the CDR circuit receives the data packet, the data signal and a clock signal synchronized with the data signal are recovered from the data packet.

Time synchronization is performed between the vehicle-mounted device and another device that is another vehicle-mounted device based on a data propagation delay time between the vehicle-mounted device and the other device. The vehicle-mounted device includes: a processing unit configured to receive, from the other device, request information that requests time information used for updating the propagation delay time, and transmit the time information to the other device; and a detection unit configured to detect an abnormality related to time synchronization, and acquire information regarding the detected abnormality.

An Ethernet bridge architecture enables timing replication. The Ethernet bridge receives data packets from a sensor (such as a video sensor) and immediately tags each data packet with a transmitter timecode. The tagged data packets are then forwarded to the appropriate receiver over the digital data network or link that may exhibit packet delivery time variations and reordering. The receiver identifies data packets including the local timecode and delays processing (display) of the data packet until a timecode local to the receiving node matches the transmitter timecode plus some delay. The receiver also restores the original order of the packets by observing packet sequence number and placing them at appropriate location in memory buffer. By delaying processing, the Ethernet bridge compensates for any variance in network latency. The delay should be greater than a worst-case delay as defined by the network architecture. The Ethernet bridge allows a distributed multi-camera and multi-display system based on high-bandwidth Ethernet infrastructure, while still using non-Ethernet sensors, displays, and application processors.

An operation method of a first communication node among a plurality of communication nodes included in an Ethernet-based vehicle network may include steps of measuring a first link delay for performing time synchronization with a second communication node included in the plurality of communication nodes; calculating a difference between the first link delay and an average value of a plurality of link delays measured before the measurement of the first link delay; comparing the calculated difference with a first threshold value for controlling a link delay measurement cycle for the second communication node; and controlling the link delay measurement cycle for the second communication node based on the comparison result.

A method for synchronizing baseband clocks in an OFDMA wireless microphone system is disclosed. An example method includes receiving a plurality of pilot subcarriers from an audio transmitter. The method also includes determining a timing offset estimate based on the pilot subcarriers. The method further includes determining a tuning value by passing the timing offset estimate through a proportional-integral controller. The method still further includes determining a modified reference signal by modifying a reference oscillator based on the tuning value. And the method yet further includes controlling (i) an audio sample clock and (ii) an antenna data clock based on the modified reference signal.

A wireless audio system including a transmitter using multiple antenna diversity techniques for different signal types is provided. Multipath performance may be optimized, along with improved spectral efficiency of the system.

A method and an apparatus for estimating synchronization of a broadcast signal in a time domain using a synchronization estimation signal through steps of: performing a correlation operation using a correlation window on a plurality of synchronization estimation signals separated to a plurality of paths and outputting a plurality of correlated signals; delaying the plurality of correlated signals to output a plurality of delayed signals; and estimating the synchronization using the plurality of delayed signals are provided.

System and method for synchronizing a plurality of nodes to a timing signal using a daisy-chain network having a forward transmission path and a reverse transmission path connected at a midpoint. Latency of the timing signal to the midpoint of the daisy-chain network is determined, a respective latency of the timing signal from the node to the midpoint of the daisy-chain network is determined, and a respective timing offset for each of the plurality of nodes is calculated. A local time-of-day counter at each of the plurality of nodes is adjusted based upon the respective timing offset of the node to synchronize the plurality of nodes to the timing signal.

The present technology relates to a data processing apparatus and a data processing method that enable correct clock synchronization by use of clock information. The data processing apparatus receives a digital broadcast signal so as to process content included in the digital broadcast signal and clock information also included therein for use in presentation synchronization on the content and sends via a transmission path the processed content and clock information to another data processing apparatus that presents the received content. On the other hand, the another data processing apparatus receives via the transmission path the content and clock information sent from the data processing apparatus so as to process presentation synchronization on the received content on the basis of the received clock information. The present technology is applicable to data processing apparatuses configured to process content, for example.

A display device including: a timing controller outputting a reference clock signal and a data packet, wherein the data packet includes a clock signal embedded in a data signal; a clock and data recovery (CDR) circuit receiving the reference clock signal and the data packet; and a display panel displaying an image based on the data packet, wherein, when the CDR circuit receives the reference clock signal, a frequency band of the reference clock signal is detected using a first internal clock signal, a parameter associated with jitter characteristics of the clock and data recovery circuit is adjusted according to the detected frequency band, and a second internal clock signal is output by adjusting a frequency of the first internal clock signal, and when the CDR circuit receives the data packet, the data signal and a clock signal synchronized with the data signal are recovered from the data packet.