The present technology relates a television apparatus that comprises circuitry configured to receive a digital broadcast signal, extract a packet including content included in the digital broadcast signal, extract time information included in a preamble of a physical layer frame, and send the time information and the packet including the content to other circuitry in the television apparatus. The television apparatus includes a transmission interface configured to interconnect the circuitry and the other circuitry. The television apparatus is further configured to process signaling that includes the time information that is comprised in the preamble of the physical layer frame in the digital broadcast signal.

An integrated circuit receiver is disclosed comprising a data receiving circuit responsive to a timing signal to detect a data signal and an edge receiving circuit responsive to the timing signal to detect a transition of the data signal. One of the data or edge receiving circuits comprises an integrating receiver circuit while the other of the data or edge sampling circuits comprises a sampling receiver circuit.

A wireless audio system including a transmitter using multiple antenna diversity techniques for different signal types is provided. Multipath performance may be optimized, along with improved spectral efficiency of the system.

In an embodiment, a receiver included in a communications system includes a channel extractor configured to segregate a received signal into a plurality of channel signals, wherein the plurality of channel signals includes a plurality of data signals; and a plurality of decoders electrically coupled to the channel extractor and configured to decode each of the plurality of channel signals into a respective plurality of decoded data beam portions.

A clock synchronization method and a communication apparatus are provided. The method includes: multiplexing a local analog clock signal and a first data signal to obtain a first multiplexed signal; sending the first multiplexed signal to a first apparatus; receiving a second multiplexed signal from the first apparatus; demultiplexing the second multiplexed signal to obtain a second data signal and a first analog clock signal, where the first analog clock signal corresponds to the local analog clock signal after it has gone through a transmission delay; obtaining a first signal based on the first analog clock signal, where the first signal is a delay compensation amount or a second analog clock signal, and the second analog clock signal is obtained by applying delay compensation to the local analog clock signal; and processing data based on the first signal to obtain the first data signal, to which delay compensation has been applied.

The present invention provides a system including a transmitter and a receiver is disclosed. The transmitter includes a first main data path and a first main strobe path, wherein the first main data path is configured to generate a plurality of data signals, the first main strobe path is configured to generate a first strobe signal, and delay amount of the first main data path and delay amount of the first main strobe path are unbalanced. The receiver includes a second main data path and a second main strobe path, wherein the second main strobe path is configured to receive the first strobe signal to generate a plurality of second strobe signals, and the second main data path is configured to receive the plurality of data signals, and uses the plurality of second strobe signals to sample the plurality of data signals to generate a plurality of sampled signals, respectively.

A memory controller having a data receiver to sample data at a sample timing using a strobe signal, wherein the data and the strobe signal are sent by a memory device in connection with a read operation initiated by the memory controller, and a strobe receiver to receive the strobe signal, wherein a phase of the strobe signal has a drift relative to a reference by an amount. The memory controller further having a monitoring circuit to monitor the strobe signal and determine the amount of the drift, and an adjustment circuit to update the sample timing of the data receiver based on the amount of drift determined by the monitoring signal.

The accuracy of an offset value is improved by correcting an error in time synchronization caused by link asymmetry. PTP packets are exchanged between a master node 3 and a slave node 4 vis a first transmission device 1 connected to the master node 3 and a second transmission device 2 corresponding to the first transmission device 1 and connected to the slave node 4. The second transmission device 2 includes: a transmission section 16 configured to transmit PTP packets for a plurality of wavelengths to the corresponding transmission device simultaneously; and a reception section 17 configured to calculate a propagation delay Dms on a path from the corresponding transmission device to the second transmission device 2 based on a difference between the arrival times of the PTP packets for the plurality of wavelengths received from the corresponding transmission device, and provide the propagation delay Dms to the slave node 4 as a correction parameter used in a process of synchronizing the time of the slave node 4.

The present technology improves synchronization of a slave node with a master node in a network using PTP packets in which the slave node is coupled to the working master node through at least one boundary node. The technology establishes a synchronization communication session between the boundary node and the slave node in which the synchronization communication session is configured to measure a first timing delay from the boundary node to the slave node, and establishes a transparent communication session between the master node and the slave node through the boundary timing node in which the transparent communication session configured to measure a second timing delay from the master node to the slave node. Using the sessions, the technology adjusts a timing delay correction factor according to the first timing delay and the second timing delay, and synchronizes the slave node with the master node according to the correction factor.

An integrated circuit receiver is disclosed comprising a data receiving circuit responsive to a timing signal to detect a data signal and an edge receiving circuit responsive to the timing signal to detect a transition of the data signal. One of the data or edge receiving circuits comprises an integrating receiver circuit while the other of the data or edge sampling circuits comprises a sampling receiver circuit.