An apparatus may include a sampling circuit configured to produce a sequence of input samples based on a continuous time input signal and a sample clock signal, the sampling phase of the sequence of input samples based on a phase control value output by a timing recovery circuit. In addition, the apparatus may include the timing recovery circuit configured to receive the sequence of input samples, detect, for a current sample of the sequence of input samples, a phase offset in the sampling phase of the sequence of input samples, the phase offset being a deviation of the sampling phase from an expected phase, and in response to detecting the phase offset, select a bandwidth for timing recovery. Further, the timing recovery circuit may generate an updated phase control value based on the selected bandwidth for timing recovery.

Disclosed is a card clock recovery system for use in an NFC card transceiver couplable to an NFC reader. The card clock recovery system has: a phase lock loop having: a phase/frequency detector, which is configured to receive a reference signal provided at an RX port of a matching network during a receiving mode of the NFC transceiver or to receive a reference signal provided at the RX port of the matching network during a transmission mode of the NFC transceiver, to receive a loop feedback signal, and to provide a phase error signal that represents a phase difference between the reference signal and the loop feedback signal; a loop filter configured to receive a corrected phase error signal that is derived from the phase error signal, and to provide a filtered corrected phase error signal; a controllable oscillator, which is configured to receive the filtered corrected phase error signal and to provide a controlled frequency output signal, which is provided as the card clock generation control signal to a card clock generation unit of an NFC card transceiver, and as the loop feedback signal, via the loop feedback line, to the phase/frequency detector. The card clock recovery system further has a phase offset correction unit, which is configured to receive the phase error signal provided by the phase/frequency detector and to provide the corrected phase error signal to the loop filter, and which has a phase error sampling unit, a phase offset computation unit, and a phase subtractor unit.

A synchronization detection method for new radio (NR) sidelink. In some embodiments, the method includes calculating a first delay compensated input signal, calculating a first correlation value, calculating a first correlation power, calculating a first weighted correlation power, and detecting a synchronization signal. The first delay compensated input signal may be based on an input signal, and an index of a first tap value. The first correlation value may be based on a first candidate sequence and the first delay compensated input signal. The first correlation power may be based on the first correlation value. The first weighted correlation power may be based on a first weighting factor, and the first correlation power. The detecting of the synchronization signal may include using the first weighted correlation power.

The present technology improves synchronization of a slave node with a master node in a network using PTP packets in which the slave node is coupled to the working master node through at least one boundary node. The technology establishes a synchronization communication session between the boundary node and the slave node in which the synchronization communication session is configured to measure a first timing delay from the boundary node to the slave node, and establishes a transparent communication session between the master node and the slave node through the boundary timing node in which the transparent communication session configured to measure a second timing delay from the master node to the slave node. Using the sessions, the technology adjusts a timing delay correction factor according to the first timing delay and the second timing delay, and synchronizes the slave node with the master node according to the correction factor.

A method for synchronizing baseband clocks in an OFDMA wireless microphone system is disclosed. An example method includes receiving a plurality of pilot subcarriers from an audio transmitter. The method also includes determining a timing offset estimate based on the pilot subcarriers. The method further includes determining a tuning value by passing the timing offset estimate through a proportional-integral controller. The method still further includes determining a modified reference signal by modifying a reference oscillator based on the tuning value. And the method yet further includes controlling (i) an audio sample clock and (ii) an antenna data clock based on the modified reference signal.

A wireless audio system including a transmitter using multiple antenna diversity techniques for different signal types is provided. Multipath performance may be optimized, along with improved spectral efficiency of the system.

In an embodiment, a receiver included in a communications system includes a channel extractor configured to segregate a received signal into a plurality of channel signals, wherein the plurality of channel signals includes a plurality of data signals; a plurality of phase shifters electrically coupled to the channel extractor and configured to decode each data signal of the plurality of data signals with a respective phase; and a plurality of time delay filters electrically coupled to the plurality of phase shifters and configured to decode each data signal of the plurality of data signals with a respective time delay, wherein the plurality of time delay filters outputs each subset of the plurality of data signals in a respective channel of the plurality of channels.

A wireless audio system including a transmitter using multiple antenna diversity techniques for different signal types is provided. Multipath performance may be optimized, along with improved spectral efficiency of the system.

A receiver circuit includes a clock lane propagating a clock signal. A self-sampled clock applies a delayed version of the clock signal to the clock signal and compensation logic controls an amount of delay of the delayed version of the clock, based on a reference voltage offset (difference) between the receiver and a transmitter. The delayed version of the clock is centered on one unit interval of the clock. An offset correction is computed as a global offset value based on a clock duty cycle error, combined with a local offset value for each data lane, and is applied to data receiver front ends.

A receiver circuit includes a clock lane propagating a clock signal. A self-sampled clock applies a delayed version of the clock signal to the clock signal and compensation logic controls an amount of delay of the delayed version of the clock, based on a reference voltage offset (difference) between the receiver and a transmitter. The delayed version of the clock is centered on one unit interval of the clock. An offset correction is computed as a global offset value based on a clock duty cycle error, combined with a local offset value for each data lane, and is applied to data receiver front ends.