A method and an apparatus are provided. The apparatus may includes a clock recovery circuit having a plurality of input latches configured to assume a first state when a first pulse is received in one or more of a plurality of input signals, combinational logic configured to provide a second pulse response to the first pulse, a delay circuit configured to produce a third pulse on a receive clock that is delayed with respect to the second pulse, a plurality of output flip-flops configured to capture the first state when triggered by the third pulse. The first state may identify which of the plurality of input signals received input pulses.

A clock generation circuit may include a reference clock generator configured to generate a pair of first reference clocks in an offset code generation mode, a correction code generator configured to generate a reference correction code according to a duty detection signal based on a phase difference between the pair of first reference clocks, and an offset code generator configured to generate an offset code based on the reference correction code and a preset reference code.

A system includes a decision feedback equalizer (DFE). The DFE includes a first summing node, a first synchronization latch, a second synchronization latch, a first feedback latch, and a first feedback shift register. The first summing node is coupled to a data input of the DFE. The first synchronization latch receives data from the first summing node. The second synchronization latch and the first feedback latch receive data from the first synchronization latch. The first feedback shift register is coupled to an output of the second synchronization latch or the first feedback latch. The first feedback shift register includes sequentially coupled shift latches. A first of the shift latches data received from the second synchronization latch or the first feedback latch and provides data to the first summing node. First alternate ones of the shift latches are configured to provide feedback data to the first summing node.

A clock generation circuit may include a reference clock generator configured to generate a pair of first reference clocks in an offset code generation mode, a triggering unit configured to generate a pair of second reference clocks from the pair of first reference clocks, a pulse detector configured to generate a duty detection signal based on a phase difference between the pair of second reference clocks, a correction code generator configured to generate a reference correction code based on the duty detection signal, and an offset code generator configured to generate an offset code based on the reference correction code and a preset reference code.

A method and an apparatus are provided. The apparatus may includes a clock recovery circuit having a plurality of input latches configured to assume a first state when a first pulse is received in one or more of a plurality of input signals, combinational logic configured to provide a second pulse response to the first pulse, a delay circuit configured to produce a third pulse on a receive clock that is delayed with respect to the second pulse, a plurality of output flip-flops configured to capture the first state when triggered by the third pulse. The first state may identify which of the plurality of input signals received input pulses.

An apparatus for tracing data from a data bus in a first clock domain operating at a first clock frequency to a trace array in a second clock domain operating at a second clock frequency, wherein the first clock frequency is lower than the second clock frequency. The apparatus includes a change detector to detect a change of the data on the data bus in the first clock domain, a trigger responsive to the change detector to send a trigger pulse to the second clock domain, pulse synchronization on the second clock domain responsive to the trigger pulse to synchronize the trigger pulse to the second clock frequency of the second clock domain by a meta-stability latch, as well as a data capture in the second clock domain responsive to the pulse synchronization to capture data from the data bus and to store the captured data in the trace array.

Systems and related methods for simultaneous high precision synchronization and syntonization of multiple sensors or clocks utilize a precision estimator that receives clock signals and time mark signals from both sensors (a reference sensor and a clock to be measured against the reference sensor). A precision time and frequency estimator determines a time offset, frequency offset, and phase offset of the measured sensor relative to the reference sensor. Associated systems can additionally determine the propagation delay between two remote subsystems connected by a communications channel. The communications channel may be a bidirectional duplexed or multiplexed channel allowing for mutual exchange of timing information along a single non-dedicated cable between sensors. Sensors may be synchronized to within 10 ps of each other without the need for THz clocks or fiber-optic cabling.

A multi-phase partial response receiver supports various incoming data rates by sampling PrDFE output values at a selected one of at least two clock phases. The receiver includes a calibration circuit that performs a timing analysis of critical data paths in the circuit, and this analysis is then used to select the particular clock phase used to latch the output values. These techniques permit the multiplexer outputs from for each phase of the partial response receiver to directly drive selection of a multiplexer for the ensuing phase, i.e., by avoiding regions of instability or uncertainty in the respective multiplexer outputs.

A low power data retiming circuit incorporates CMOS components in certain sections that operate at a lower frequency in comparison to certain other sections that use components based on bipolar technology for operating at a relatively higher frequency. The data retiming circuit includes a clock recovery circuit wherein a voltage controlled oscillator provides a recovered clock to a clock generator circuit for generating a latched clock that is provided to a phase detector and a data serializer. The data serializer operates as a synchronous multiplexer for generating a retimed data output signal from a pair of latched data input signals. The phase detector and the data serializer operate in a half-rate mode wherein high and low voltage levels of the latched clock are used for clocking data. The half-rate mode of operation permits the use of a clock frequency that is half that of an input data rate.

A clock generation circuit may include a reference clock generator configured to generate a pair of first reference clocks in an offset code generation mode, a triggering unit configured to generate a pair of second reference clocks from the pair of first reference clocks, a pulse detector configured to generate a duty detection signal based on a phase difference between the pair of second reference clocks, a correction code generator configured to generate a reference correction code based on the duty detection signal, and an offset code generator configured to generate an offset code based on the reference correction code and a preset reference code.