The present invention relates to a method for synchronising a node in a deterministic mesh network, in particular a network of sensors using a channel hopping (TSCH) transmission medium access mode. Each node measures the successive synchronisation offsets of its local clock in relation to those of neighbour nodes with which it enters into communication, the measurement being carried out by detecting a reception event of a packet transmitted by the neighbour node or an acknowledgement of a packet transmitted by said node to the neighbour node. The node estimates from these synchronisation offsets, a synchronisation offset for the timeslot and corrects its local clock by a fraction of the synchronisation offset thus estimated. Said fraction may be determined by means of multi-agent reinforcement learning (MARL), each agent being associated with a node of the network.

A memory controller includes a clock signal generator generating a clock signal; a first data receiving circuit receiving a serial signal having a plurality of logic values from a memory, using the serial signal to compensate for a phase error of the clock signal, and generating a phase-compensated clock signal as a first clock signal; and at least one second data receiving circuit receiving data from the memory, receiving the first clock signal from the first data receiving circuit, and using the first clock signal to recover the data.

A data transmission device of an embodiment includes a buffer, a first determination circuit, a first flip-flop, a second flip-flop, and a second determination circuit. The buffer holds input data of a predetermined bit width. The first determination circuit determines whether or not the input data is held in the buffer. The first flip-flop receives output of the first determination circuit as input and operates at one of a rising edge and a falling edge of a second clock signal which is asynchronous with the first clock signal. The second flip-flop receives output of the first flip-flop as input and operates at another of the rising edge and the falling edge of the second clock signal. The second determination circuit determines an error based on a request signal which is synchronized with the second clock signal and output of the second flip-flop.

The present application discloses an asynchronous sampling architecture and a chip. The asynchronous sampling architecture is configured to receive a first input data string from the peer end, and the asynchronous sampling architecture includes: a first register, configured to buffer a first input data string, wherein the first input data string is written into the first register according to a peer end clock of the peer end; and a gated clock generation unit, configured to generate a gated clock, wherein the frequency of the gated clock is the same as the frequency of the peer end clock, and the first input data string is read out as a first output data string from the first register according to the gated clock.

The present invention relates to a multi-channel IM-DD optical transceiver comprising at least one transmitter and a receiver, and a method for equalizing input samples at an adjusted sampling phase using a quality parameter linearly proportional to a BER. The data transmission and reception use a single master channel and slave channels, which have a baud rate equal to or lower than the baud rate of the master channel. A reliable and identical clocking of all the channels is obtained through either the receiver clock of the master channel when they are received from a single transmitter or a reference clock whose frequency is higher than the highest clock frequency amongst all the channels when they are received from a combination of transmitters. An enhanced timing recovery circuit is also provided to select optimized finite impulse response filters, calculate filter coefficients and generate the receiver clock of the master channel.

An electronic device comprises a first circuit portion comprising one or more components, including a first counter, which are clocked by a first clock signal. The first circuit portion is arranged to receive a data stream comprising a plurality of data signals. A second circuit portion comprises one or more components clocked by a second clock signal and a second counter not clocked by the second clock signal. The first clock signal is not synchronised to the second clock signal. The second circuit portion is arranged to: receive samples of the data stream from the first circuit portion at a sample rate and to time-stamp each received sample with a count value of the second counter. The second circuit portion increments the count value of the second counter by a predetermined increment value for each received sample.

A radio receiver device, arranged to receive a radio signal modulated with a plurality of data symbols, comprises an analogue-to-digital converter that is clocked by a first clock signal and is arranged to receive the radio signal and produce a digital signal. A digital circuit portion, arranged to receive the digital signal produced by the analogue-to-digital converter, comprises digital processing units that are clocked by a second clock derived from the first clock and arranged to process the digital signal and produce an output signal at an output sample rate. A counter, clocked by the second clock, counts a number of samples at the output sample rate. A network timer clocked by a reference of a network clock produces a receiver enable flag which is synchronised to the first clock. The counter is enabled only when the synchronised flag is set. The counter is arranged to set a trigger flag when the number of samples exceeds a predetermined threshold. A buffer is arranged to receive the output signal and is enabled only when the trigger flag is set.

A memory controller includes a clock signal generator generating a clock signal; a first data receiving circuit receiving a serial signal having a plurality of logic values from a memory, using the serial signal to compensate for a phase error of the clock signal, and generating a phase-compensated clock signal as a first clock signal; and at least one second data receiving circuit receiving data from the memory, receiving the first clock signal from the first data receiving circuit, and using the first clock signal to recover the data.

A variable delay interface configured to introduce a controllable, variable delay between a radio equipment controller and a radio equipment is provided. The interface includes a variable rate change filter, VRCF, having a signal input, a signal output and a rate control input. The VRCF is configured to receive a rate control signal at the rate control inputs and sample an input signal received at the signal input at a sampling rate controlled by a rate control signal to produce a VRCF output signal. The sampling rate is one of greater than and less than a sampling rate of the input signal. The VRCF has a first delay. The interface includes a first in first out, FIFO, buffer having an input and an output, the FIFO buffer configured to store samples of the VRCF output signal received at the FIFO buffer.

A FIFO apparatus includes write registers, a first control circuit, a multiplexer, and a second control circuit. The write registers are for receiving an input signal and the first clock signal, and outputting first outputs to a multiplexer. The first control circuit is for receiving a first clock signal, generating a first toggling pulse, and enabling the write registers according to a sequence. The second control circuit is for controlling the multiplexer according to the first toggling pulse and a second clock. The multiplexer outputs a second output according to the sequence. The first and second clock signals have a first delay time and a second delay time, respectively. Difference between the first and second delay times is equal to M cycle(s) of the first clock signal, and a number of the write registers is equal to or larger than M.