Forwarding points in time of a clock over a clock boundary is performed by launching the points in time into a buffer, such as a FIFO, in the first clock domain. The oldest point in time is fed into a FIFO or delay line in the other clock domain, which FIFO or delay line comprises a plurality of received points in time, which are shifted through the FIFO or delay line over time. An estimate of a point in time in the second clock domain is derived from a plurality of the points in time in the delay line/FIFO, such as from a mean value thereof. This point in time may be compensated for a known delay in order for this determined point in time to be identical to or close to an actual point in time of the first clock in the first clock domain.

A fill level control apparatus configured to control the average fill level of an asynchronous first-in-first-out, FIFO, the fill level control apparatus comprising an offset calculation unit adapted to or configured to calculate the offset between a programmable target average fill level and the current average fill level of the FIFO and an adjustment unit adapted to or configured to adjust continuously the empty rate of the FIFO in response to the calculated offset to keep the average fill level of the FIFO constant.

A method of operating an interface device including a first elastic buffer is provided. The method of operating the interface device includes performing a link equalization operation, checking a transmission mode of the interface device, and determining a transmission parameter of the interface device based on a status of the first elastic buffer or a status of a second elastic buffer included in another interface device communicating with the interface device when the transmission mode is a transmission parameter adjustment mode.

An electronic circuit for converting a signal between digital and analog in a burst mode, including a processor configured to utilize a synchronizing clock signal, a converter configured to convert a signal data between digital and analog using a converter clock signal, a phase comparator configured to determine a phase relationship between the synchronizing clock signal and the converter clock signal, and a digital signal processor coupled to the phase comparator and configured to receive an information about the phase relationship, wherein the digital signal processor is configured to apply a delay to the signal data being exchanged between the processor and. The synchronizing clock signal and the converter clock signal have a predetermined frequency relationship.

A parallel transfer rate converter inputs first parallel data with number of samples being S1 pieces in synchronism with a first clock, and outputs second parallel data with number of samples being S2=S1(m/p) pieces (p is an integer equal to or larger than 1) in synchronism with a second clock having a frequency which is p/m times of a frequency of the first clock. A convolution operation device inputs the second parallel data in synchronism with the second clock, generates third parallel data with number of samples being S3=S2(n/m) pieces (S3 is an integer equal to or larger than 1) by executing a convolution operation with a coefficient indicating a transmission characteristic to the second parallel data, and outputs the third parallel data in synchronism with the second clock.

Systems and methods are provided in which a wireless receiver can be configured to digitally synchronize a receive sampling rate to a transmit sampling rate, and may include a digital interpolator controlled by a timing control unit with a timing offset estimator. The timing control unit can be configured to calculate and output parameters to the digital interpolator. The digital interpolator can include a sample buffer followed by a fractional delay filter. Output parameters to the digital interpolator can include a fractional delay timing offset signal of the receiver relative to a transmitter timing signal and a buffer pointer control signal to control a position of the read pointer relative to a write pointer to compensate for subsample timing offset. The timing offset estimator can be configured to calculate and provide to the timing control unit a sampling period ratio control word and an instantaneous timing offset control word.

A wafer-level package includes a first die and a second die that are wafer-level packaged. The first die has a first clock source. The second die has a second clock source. The first clock source generates a clock shared by the first die and the second die. The second clock source, however, does not generate a clock used by any of the first die and the second die.

An FIR filter convolutes sampled data obtained by sampling a reception signal with tap coefficients. A phase difference detector detects a phase difference between a synchronization timing of a signal waveform estimated from an output signal of the FIR filter and a sampling timing of the output signal. A tap coefficient adjuster adjusts the tap coefficients so as to reduce the phase difference detected by the phase difference detector and causes the sampling timing of the output signal of the FIR filter to track the synchronization timing.

The invention concerns a circuit for transferring a data from one clock domain to another clock domain, the circuit comprising: a digital circuit configured to generate a data signal synchronized with a source clock signal, and to receive such data by sampling the data signal synchronized with a target clock signal; a phase comparator which is configured to determine a phase relationship between the source clock signal and the target clock signal; and a data signal synchronization circuit configured to receive data signal transitions that are synchronized with the source clock signal, and to provide a synchronized data signal transitions of which are synchronized with the target clock signal.

Methods, systems, and apparatus for inserting a re-timer signal between a transmitter and a receiver, including receiving, from the transmitter, an input data signal having encoded words, where each encoded word of the encoded words has a word length of a predetermined number of bits; generating, by a re-timer and based on the input data signal, a regenerated clock signal and an output data signal; determining, based on the regenerated clock signal, a timing difference between the input data signal and the output data signal of the re-timer; and applying, by the re-timer and based on the timing difference between the input data signal and the output data signal, a delay to the input data signal to generate a delayed output data signal, such that a timing difference between the input data signal and the delayed output data signal corresponds to N word lengths.