A receiver is equipped with an adaptive phase-offset controller and associated timing-calibration circuitry that together shift the timing for a data sampler and a digital equalizer. The sample and equalizer timing is shifted to a position with less residual inter-symbol interference (ISI) energy relative to the current symbol. The shifted position may be calculated using a measure of signal quality, such as a receiver bit-error rate or a comparison of filter-tap values, to optimize the timing of data recovery.

The controller includes a first equalizer, a first detector, a second detector, a multiplexer, a data clock generator, and a second equalizer. The first equalizer is configured to receive and equalize the input data. The first detector is configured to detect optimum phase of the input data. The optimum phase of the input data represents the input data peak. The second detector is configured to generate an envelope data according to the input data and detect peak of envelop with respect to sampling phase. The data clock generator is configured to generate the recovered data clock. The second equalizer is configured to generate the recovered data. The multiplexer is configured to generate an offset value according to the input data peak and the envelope data peak. The offset value represents the recovered data clock having an optimum sampling frequency and an optimum sampling phase.

A multi-PAM equalizer receives an input signal distorted by inter-symbol interference (ISI) and expressing a series of symbols each representing one of four pulse amplitudes to convey two binary bits of data per symbol. High-order circuitry resolves the most-significant bit (MSB) of each two-bit symbol, whereas low-order circuitry 115 resolves the immediate least-significant bit (LSB). The MSB is used without the LSB for timing recovery and to calculate tap values for both MSB and LSB evaluation.

At least some aspects of the present disclosure provide for a method. In at least one example, the method includes applying first equalization to a received data signal to generate an equalizer signal and comparing the equalized signal to each of a plurality of reference voltages for a predetermined period of time per respective reference voltage to generate a comparison result. The method further includes determining a plurality of counts with each count of the plurality of counts uniquely corresponding to a number of rising edges in the comparison result for each of the plurality of reference voltages. The method further includes comparing at least one of the plurality of counts to at least another of the plurality of counts to determine a relationship among the plurality of counts and applying second equalization to the received data signal based on the determined relationship among the plurality of counts.

A method and structure for tap centering in a coherent optical receiver device. The center of gravity (CG) of the filter coefficients can be used to evaluate a proper convergence of a time-domain adaptive equalizer. However, the computation of CG in a dual-polarization optical coherent receiver is difficult when a frequency domain (FD) adaptive equalizer is adopted. In this case, the implementation of several inverse fast-Fourier transform (IFFT) stages is required to back time domain impulse response. Here, examples of the present invention estimate CG directly from the FD equalizer taps and compensate for an error of convergence based off of the estimated CG. This estimation method and associated device architecture is able to achieve an excellent tradeoff between accuracy and complexity.

A method and structure for a coherent optical receiver device. Timing recovery (TR) is implemented after channel dispersion (i.e., chromatic dispersion (CD) and polarization mode dispersion (PMD)) compensation blocks. This architecture provides both improves performance and reduces power consumption of the device. Also, a TR loop is provided, enabling computing, by an error evaluation module, a first sampling phase error (SPE) and computing, by a timing phase information (TPI) module coupled to the error evaluation module, a second SPE from a plurality of CD equalizer taps PMD equalizer taps. The first and second SPE are combined into a total phase error (TPE) in a combining module, and the resulting TPE is filtered by a timing recovery (TR) filter coupled to an interpolated timing recovery (ITR) module and the combining module. The ITR module then synchronizes an input signal of the coherent optical receiver according to the TPE.

A receiver applies a calibration method to compensate for skew between input channels. The receiver skew is estimated by observing the coefficients of an adaptive equalizer which adjusts the coefficients based on time-varying properties of the multi-channel input signal. The receiver skew is compensated by programming the phase of the sampling clocks for the different channels. Furthermore, during real-time operation of the receiver, channel diagnostics is performed to automatically estimate differential group delay and/or other channel characteristics based on the equalizer coefficients using a frequency averaging or polarization averaging approach. Framer information can furthermore be utilized to estimate differential group delay that is an integer multiple of the symbol rate. Additionally, a DSP reset may be performed when substantial signal degradation is detected based on the channel diagnostics information.

A data equalization system includes a data clock input configured to receive a clock signal. There is an input node operative to receive a data signal of transmission symbols that change state synchronously with the clock signal. There is a first tap coupled to the input node. A second tap is configured to receive a variation of the data signal. At least one of a weight of the first tap or a weight of the second tap is modulated by a dynamic control parameter that repeats synchronously with each transmission symbol.

A data receiver circuit includes a summer circuit configured to receive an input signal that encodes multiple data symbols, and combine the input signal with a feedback signal to generate an equalized input signal, which is used to generate a clock signal. The data receiver circuit also includes multiple data slicer circuits that sample, using the clock signal and multiple voltage offsets, to generate multiple samples for a particular data symbol. A precursor compensation circuit included in the data receiver circuit may generate an output value for the particular data symbol using the multiple samples. The data receiver circuit also includes a post cursor compensation circuit that generates the feedback signal using at least one of the multiple samples and a value of a previously received sample.

A system and method for data sampler drift compensation in a SerDes receiver. Off-data values are received at a drift compensation engine from a plurality of data value selectors coupled to one of a plurality of data sampler pairs of a speculative Decision Feedback Equalizer (DFE) of a SerDes receiver. A drift compensation value for each of the data samplers is generated by the drift compensation engine based upon the off-data values received from each of the plurality of data value selectors and, a sampling level of each of the data samplers of the plurality of data sampler pairs of the DFE is adjusted based upon the drift compensation value from the drift compensation engine.