A present technology relates to a transmission device, a transmission method, a reception device, a reception method, and a program that can improve reception performance of a frame to which a preamble is added. A transmission device of one aspect of the present technology generates a preamble including a sequence [d d . . . d d] having iteration of a sequence d that is one of sequences a and b that are Golay complementary sequences, followed by an inverted sequence of the sequence d, and including a signal sequence in which a maximum value of an absolute value of a side lobe level of cross correlation between a sequence [d d d] and a sequence [d d] is 25 or less. The generated preamble is added to data to be transmitted in units of frames. The present technology can be applied to a device that transmits and receives data via a wireless transmission path.

A method and structure for a coherent optical receiver device. Timing recovery (TR) is implemented after channel dispersion (i.e., chromatic dispersion (CD) and polarization mode dispersion (PMD)) compensation blocks. This architecture provides both improves performance and reduces power consumption of the device. Also, a TR loop is provided, enabling computing, by an error evaluation module, a first sampling phase error (SPE) and computing, by a timing phase information (TPI) module coupled to the error evaluation module, a second SPE from a plurality of CD equalizer taps PMD equalizer taps. The first and second SPE are combined into a total phase error (TPE) in a combining module, and the resulting TPE is filtered by a timing recovery (TR) filter coupled to an interpolated timing recovery (ITR) module and the combining module. The ITR module then synchronizes an input signal of the coherent optical receiver according to the TPE.

A receiver is equipped with an adaptive phase-offset controller and associated timing-calibration circuitry that together shift the timing for a data sampler and a digital equalizer. The sample and equalizer timing is shifted to a position with less residual inter-symbol interference (ISI) energy relative to the current symbol. The shifted position may be calculated using a measure of signal quality, such as a receiver bit-error rate or a comparison of filter-tap values, to optimize the timing of data recovery.

A method and structure for signal propagation in a coherent optical receiver device. Asynchronous equalization helps to reduce complexity and power dissipation, and also improves the robustness of timing recovery. However, conventional devices using inverse interpolation filters ignore adaptation algorithms. The present invention provides for forward propagation and backward propagation. In the forward case, the filter input signal is forward propagated through a filter to the adaptation engine, while, in the backward case, the error signal is backward propagated through a filter to the asynchronous domain. Using such forward and backward propagation schemes reduces implementation complexity while providing optical device performance.

A system for retiming a multi-level signal that forms an eye diagram when plotted, such as a PAM4 signal that includes an equalizer configured to create an equalized signal and a first amplifier configured to amplify the equalized signal, responsive to a first amplifier control signal, to create a first amplified signal, and a second amplifier configured to amplify the equalized signal, responsive to a second amplifier control signal, to create a second amplified signal. An eye monitor processes the equalized signal, the first amplified signal, and the second amplified signal to create a first retiming clock phase signal and a second retiming clock phase signal, which control sampling times for flip-flops. One or more delays and one or more emphasis modules are configured to delay and introduce emphasis into an output from the flip-flops, the resulting signals are combined in a summing junction to create the retimed signal.

A multi-PAM equalizer receives an input signal distorted by inter-symbol interference (ISI) and expressing a series of symbols each representing one of four pulse amplitudes to convey two binary bits of data per symbol. High-order circuitry resolves the most-significant bit (MSB) of each two-bit symbol, whereas low-order circuitry 115 resolves the immediate least-significant bit (LSB). The MSB is used without the LSB for timing recovery and to calculate tap values for both MSB and LSB evaluation.

A serial data receiver circuit included in a computer system may include both an analog and an ADC-based receiver circuit. A front-end circuit generates different equalized signals based on received signals that encode a serial data stream that includes multiple data symbols. During startup of a communication channel, phase information generated by the analog receiver circuit may be used to generate clock signals for the ADC-based receiver circuit. After a period of time, the ADC-based receiver circuit can generate its own phase information to be used in the generation of the clock signals.

A method, for calibrating signal processing devices in an interface circuit coupled to a host device, comprises: negotiating with the host device in a link up process about an operation mode for the interface circuit to operate in a calibration procedure; and calibrating a characteristic value of a first signal processing device and a characteristic value of a second signal processing device in the calibration procedure. The first signal processing device is disposed on a receiving signal processing path and configured to process a received signal and the second signal processing device is disposed on a transmitting signal processing path and configured to process a transmitting signal, and the interface circuit is configured to operate based on the operation mode in the calibration procedure.

A coherent optical receiver includes equalizer circuitry having a plurality of taps, the equalizer circuitry being configured to receive an input signal and compensate for polarization mode dispersion affecting the input signal to generate a compensated input signal. The coherent optical receiver further includes error evaluation circuitry configured to calculate a determinant of a frequency-domain (FD) coefficient-based matrix using a plurality of tap signals from among the plurality of taps, adjust an error of convergence of the compensated input signal to generate an adjusted input signal, and iteratively adjust the determinant of the FD coefficient-based matrix based on the adjusted input signal to minimize the error of convergence.

An equalizer circuit includes: an addition circuit configured to add an input signal and a compensation signal; a comparison circuit configured to compare an output signal of the addition circuit; a plurality of first latch circuits configured to hold an output signal of the comparison circuit, the plurality of first latch circuits being connected in cascade; a selection circuit configured to select and output one of output signals of the comparison circuit and the plurality of first latch circuits; a second latch circuit configured to hold an output signal of the selection circuit; and a digital analog conversion circuit configured to generate the compensation signal, based on an output signal of the second latch circuit.