A receiver device implements enhanced data reception with edge-based clock and data recovery such as with a flash analog-to-digital converter architecture. In an example embodiment, the device implements a first phase adjustment control loop, with for example, a bang-bang phase detector, that detects data transitions for adjusting sampling at an optimal edge time with an edge sampler by adjusting a phase of an edge clock of the sampler. This loop may further adjust sampling in received data intervals for optimal data reception by adjusting the phase of a data clock of a data sampler such a flash ADC. The device may also implement a second phase adjustment control loop with, for example, a baud-rate phase detector, that detects data intervals for further adjusting sampling at an optimal data time with the data sampler.

A clock data recovery (CDR) mechanism qualifies symbols received from the data detector prior to using those symbols to compute a timing gradient. The disclosed CDR mechanism analyzes one or more recently received symbols to determine whether the current symbol should be used in computing the time gradient. When configured with a Mueller-Muller phase detector, the timing gradient for the received signal is set to zero if the current symbol is a 2 or a +2 and the previous symbol is non-zero. Otherwise, the Mueller-Muller timing gradient is evaluated in the traditional manner. When configured with a minimum mean-squared error phase detector, the timing gradient for the received signal is set to zero if the previous symbol is non-zero. Otherwise, the minimum mean-squared error timing gradient is evaluated in the traditional manner.

A receiver system that includes a clock and data recovery (CDR) system for aligning a local clock signal to an incoming data signal to extract correct timing information from the incoming data signal is provided. A timing error detector generates an output phase error signal representing the phase difference between the incoming data signal and the local clock signal. The timing error detector determines the phase difference according to recovered symbols and the difference between the recovered symbols and digital samples of the incoming data signal. The digital samples of the incoming data signal include intersymbol interference. The output timing information is suitable for aligning the local clock signal to the incoming data signal.

A system for data and clock recovery includes a timing error detector, a phase detector, and a phase increment injector. The phase increment injector may be used to determine an increment to affect an output of the phase detector or a clocking element. A sign of the increment is determined from a sign or direction of an accumulated version of a clock and data recovery gradient value.

The present invention relates to an adaptive synchronization device for demodulating a signal in linear modulation (x). The device functions from a sampled version of the signal (x). The device being characterized in that it comprises: at least one synchronization module (F) comprising: at least one first sub-module (F.sub.n) arranged to deliver a first output signal (y) from the input signal (x) received at a period (T) less than the value (I) with (B) the bandwidth of the input signal (x); this first sub-module (F.sub.n) is capable of compensating a transmission delay of the input signal (x) by estimation of the propagation delay () between a transmitter and a receiver of a transmission medium; this first sub-module adapts the rate at its output to one sample per symbol; at least one second sub-module (F.sub.u) arranged to deliver a corrective () to be applied to the current estimation of the delay (), from an error term (w) defining the decision error of the device and the influence of the processings downstream of the first sub-module (F); at least one correction module of transmission imperfections (H), disposed downstream of the synchronization module (F) and forming a correction chain of transmission imperfections of the first output signal (y) received by this module (H) at the rhythm T, and comprising: at least one first sub-module (H.sub.n) arranged to deliver a second output signal (z) at the rhythm (T) estimating a stream of emitted symbols (ai); at least one second sub-module (H.sub.p) configured to deliver the error term (w), by application of a correction to an error term (v) for estimation of symbols to consider the influence of the processings included in the first sub-module (H.sub.n).

[00001]$\begin{array}{cc}\left(\frac{1}{B}\right)& \left(I\right)\end{array}$

A multi-PAM equalizer receives an input signal distorted by inter-symbol interference (ISI) and expressing a series of symbols each representing one of four pulse amplitudes to convey two binary bits of data per symbol. High-order circuitry resolves the most-significant bit (MSB) of each two-bit symbol, whereas low-order circuitry 115 resolves the immediate least-significant bit (LSB). The MSB is used without the LSB for timing recovery and to calculate tap values for both MSB and LSB evaluation.

There are provided examples of receivers, controller units and related methods, wherein one receiver includes: an adjustable sample provider configured to provide samples of an input signal using an adjustable sample timing; a feedback path configured to provide a feedback signal to the adjustable sample provider on the basis of a timing error, wherein the feedback path includes a loop filter configured to provide sample timing information to the adjustable sample provider; and a replacement value provider configured to provide a replacement sample timing information replacing the sample timing information provided by the feedback path when an input signal does not fulfil a predetermined requirement for a feedback-based sample timing adaptation, wherein the replacement value provider is configured to provide the replacement sample timing information considering a timing error information, or a quantity derived from the timing error information, over a longer time period when compared to a time period considered by the loop filter for a provision of the sample timing information.

Described is an apparatus which comprises: a Variable Gain Amplifier (VGA); a set of samplers to sample data output from the VGA according to a clock signal; and a Clock Data Recovery (CDR) circuit to adjust phase of the clock signal such that magnitude of a first post-cursor signal associated with the sampled data is substantially half of a magnitude of a primary cursor tap associated with the sampled data.

A receiver system that includes a clock and data recovery (CDR) system for aligning a local clock signal to an incoming data signal to extract correct timing information from the incoming data signal is provided. A timing error detector generates an output phase error signal representing the phase difference between the incoming data signal and the local clock signal. The timing error detector determines the phase difference according to recovered symbols and the difference between the recovered symbols and digital samples of the incoming data signal. The digital samples of the incoming data signal include intersymbol interference. The output timing information is suitable for aligning the local clock signal to the incoming data signal.

In one embodiment, a time-interleaved analog-to-digital convertor (ADC) system, includes an array of ADCs to sample respective analog voltages at sampling times indicated by respective clock signals and to output corresponding digital values, phase generator circuitry to provide multiple, different phase-shifted clock signals for driving the respective sampling times of the ADCs, and a clock and data recovery circuit including ADC-specific first-order loop filters to derive respective ADC-specific average phase error corrections, and a shared loop filter to derive a shared average phase error correction over the array of ADCs and wherein the phase generator circuitry is coupled to provide corrected respective ones of the phase-shifted clock signals responsively to both respective ones of the ADC-specific average phase error corrections derived by respective ones of the first-order loop filters, and the shared average phase error correction derived by the shared loop filter.