A network communications receiver and a method of operating the same in symbol timing recovery and equalization adaptation. A data converter samples a received analog signal at an initialization frequency higher than the symbol frequency of the received signal, and converts the samples to a digital sample stream. A decision feedback equalizer including a digital filter with one or more tap weights is adapted, and an error measurement obtained from the output of the decision feedback equalizer. In response to the error measurement crossing an error threshold value, a timing loop including timing error detection is initiated to adjust the phase of the sampling clock applied to the data converter.

A serial data receiver circuit included in a computer system may include both an analog and an ADC-based receiver circuit. A front-end circuit generates different equalized signals based on received signals that encode a serial data stream that includes multiple data symbols. During startup of a communication channel, phase information generated by the analog receiver circuit may be used to generate clock signals for the ADC-based receiver circuit. After a period of time, the ADC-based receiver circuit can generate its own phase information to be used in the generation of the clock signals.

The invention relates to a method and timing recovery circuit for recovering a sampling clock from a serial data stream encoded using Pulse-Amplitude-Modulation, comprising: applying a filter pattern decoder to detected symbol sequence at more than two adjacent data symbols, particularly to the detected symbol patterns of four adjacent samples {circle around (y)}(k2), {circle around (y)}(k1), {circle around (y)}(k), {circle around (y)}(k+1), and calculating an estimated phase error e(k).

A clock recovery circuit may include: a data slicer configured to output data values based on an input signal, a first error block, a phase adjustment loop including: a first error slicer configured to generate a first error signal based on a comparison of a threshold voltage and an input voltage, wherein the first error block is configured to selectively output the first error signal in response to a first pattern in the output data values, a second error block configured to selectively output the first error signal in response to a second pattern in the output data values, and a voltage threshold modification circuitry configured to adjust the threshold voltage based on output of the second error block, a voltage-controlled oscillator, wherein the data slicer and the first error slicer are clocked based on output of the voltage-controlled oscillator.

System and method of timing recovery to achieve sampling phase optimization with aid of equalization adaptation. For equalizer filter, the offset between a current Center of Filter (COF) value and a nominal COF value is used as a measure for a clock phase correction resulted from an adaptive equalization process. A COF may be defined as a function of two selected tap weights or equal to a selected tap weight. The nominal COF value can be dynamically adapted based on the real-time sampling phase error. The tap weights of the equalizer filter are adjusted to decrease the offset, e.g., by interpolating/extrapolating selected tap weights based on the offset. By using sampling phase error as a feedback for COF_nom updating and so for equalization adaptation, the clock delay correction contributed by the adaptive equalization process is advantageously controlled to benefit sampling phase optimization.

A receiver includes: an A/D converter that performs an analog digital conversion of an input signal; an equalizer that equalizes an output from the A/D converter, eliminates inter code interference and obtains a data output; a timing recovery part that generates a recovery clock from the data output of the equalizer; a detector that detects the timing when an input signal varies from a no-signal state and has reached a predetermined threshold; and an initial phase setting part that sets as the initial phase of the recovery clock by the timing recovery part, a timing when the predetermined time has elapsed after the timing detected by the detector.

In accordance with embodiments disclosed herein, there is provided systems and methods for jitter sensing and adaptive control of parameters of clock and data recovery (CDR) circuits. A receiver component includes an adaptive CDR loop dynamic control circuit. The adaptive CDR loop dynamic control circuit is to detect first sinusoidal jitter at a first frequency and a first amplitude and update parameters of the CDR circuit to a first plurality of values based on the first frequency and the first amplitude. The adaptive CDR loop dynamic control circuit is further to detect second sinusoidal jitter at a second frequency and a second amplitude and update the parameters of the CDR circuit to a second plurality of values based on the second frequency and the second amplitude. The first sinusoidal jitter is in a first incoming data signal and the second sinusoidal jitter is in a second incoming data signal.

An apparatus for providing timing recovery in high speed links includes: an error sampler receiving an input signal and sampling the input signal; a phase detector comprising an error slicer; and a voltage-controlled oscillator (VCO). The error slicer generates an error signal corresponding to the input signal with respect to a voltage threshold. The phase detector generates a bit data corresponding to the error signal. The VCO changes a frequency of an output signal based on the bit data and locks the frequency at a phase in which an average of a plurality of input signals is equal to the voltage threshold.

Described is an apparatus which comprises: a Variable Gain Amplifier (VGA); a set of samplers to sample data output from the VGA according to a clock signal; and a Clock Data Recovery (CDR) circuit to adjust phase of the clock signal such that magnitude of a first post-cursor signal associated with the sampled data is substantially half of a magnitude of a primary cursor tap associated with the sampled data.

A receiver device implements enhanced data reception with edge-based clock and data recovery such as with a flash analog-to-digital converter architecture. In an example embodiment, the device implements a first phase adjustment control loop, with for example, a bang-bang phase detector, that detects data transitions for adjusting sampling at an optimal edge time with an edge sampler by adjusting a phase of an edge clock of the sampler. This loop may further adjust sampling in received data intervals for optimal data reception by adjusting the phase of a data clock of a data sampler such a flash ADC. The device may also implement a second phase adjustment control loop with, for example, a baud-rate phase detector, that detects data intervals for further adjusting sampling at an optimal data time with the data sampler.