A receiver capable of receive and process data signals of multiple baud rates by using an equalizer that is disposed upstream of a decimator. The receiver includes an equalizer coupled to an output of an analog-to-digital converter (ADC), and a decimator couple to the output of the equalizer. The ADC and the equalizer both operate in full rates even in the case of lower data rate, e.g., half or quarter data rate. As the equalizer inherently can inherent remove high frequency noise as well as perform equalization, it practically functions as a low pass filter (LPF). Thereby, there is no need to introduce an extra dedicate LPF upstream of the decimator. This can advantageously and significantly simplify circuitry design and reduce latency.

A receiver including an equalizer disposed upstream of a decimator and capable of effectively preventing undesirable interaction between equalization adaptation and the overall timing recovery loop in cases of various data rates. The equalizer operates in a full operation rate even in the case of a lower-than-full data rate, e.g., half or quarter data rate. For input analog signal having 1/M of the full data rate (M>1), M or more Center of Filter (COF) values are determine. Each COF may be derived from a function of a respective set of tap weights and compared with a corresponding nominal COF to obtain a COF offset. The resultant COF offsets are used as indications of clock phase correction caused by equalization adaptation to adjust a set of selected tap weights. The taps selected for adjustment encompass at least M samples to correctly indicate the COF offset associate with one symbol.

Described is an apparatus which comprises: a Variable Gain Amplifier (VGA); a set of samplers to sample data output from the VGA according to a clock signal; and a Clock Data Recovery (CDR) circuit to adjust phase of the clock signal such that magnitude of a first post-cursor signal associated with the sampled data is substantially half of a magnitude of a primary cursor tap associated with the sampled data.

A test device includes a comparison circuit configured to receive a plurality of input signals and generate a plurality of comparison signals based on the plurality of input signals; and a field programmable gate array (FPGA) configured to recover clock data, based on the plurality of comparison signals, wherein the FPGA includes a sampling circuit configured to generate a plurality of sample data signals by sampling the plurality of comparison signals; an edge extraction circuit configured to generate a plurality of edge data signals, based on logic values of bits in the plurality of sample data signals; an edge combining circuit configured to generate combined edge data by performing a logic operation on the plurality of edge data signals; and a filter circuit configured to recover the clock data by filtering the combined edge data.

The present invention is directed to data communication. More specifically, embodiments of the present invention provide a transceiver that processes an incoming data stream and generates a recovered clock signal based on the incoming data stream. The transceiver includes a voltage gain amplifier that also performs equalization and provides a driving signal to track and hold circuits that hold the incoming data stream, which is stored by shift and holder buffer circuits. Analog to digital conversion is then performed on the buffer data by a plurality of ADC circuits. Various DSP functions are then performed over the converted data. The converted data are then encoded and transmitted in a PAM format. There are other embodiments as well.

A system and method for Feed Forward Equalizer (FFE)-Aided Clock Data Recovery (CDR) to calibrate phase offset and enhance gain in baud rate sampling phase detector is provided. In an embodiment, a clock data recovery (CDR) apparatus includes an incremental feed forward equalizer (INC-FFE) in a CDR path and a calibration component in an equalization path, the calibration component connected to the INC-FFE, the calibration component configured to adjust FFE coefficients for the INC-FFE according to a phase code (PC) index in a PC index table and one of a signal-to-noise-ratio (SNR) and a bit error rate (BER) of a sampled signal, wherein the PC index table comprises adjustment values for the FFE coefficients, and wherein the PC index is linearly related to a sampling phase.

A method for timing recovery for a high-speed data transmission system may be provided. The method comprises receiving an analog input signal at an ADC and passing processed digital signal samples to a Viterbi detector. The method also comprises receiving at least one processed signal sample and at least two sets of at least one candidate symbol each from the Viterbi detector and/or the processed signal samples by timing error detectors and forwarding output digital signals of the timing error detectors via loop filters to related multiplexers. Furthermore, the method comprises selecting one digital signal from each of the multiplexers using a select signal generated by the Viterbi detector, and deriving a control signal controlling a sampling clock of the analog-to-digital converter by at least one of the selected digital signals from the multiplexers.

In accordance with embodiments disclosed herein, there is provided systems and methods for jitter sensing and adaptive control of parameters of clock and data recovery (CDR) circuits. A receiver component includes an adaptive CDR loop dynamic control circuit. The adaptive CDR loop dynamic control circuit is to detect first sinusoidal jitter at a first frequency and a first amplitude and update parameters of the CDR circuit to a first plurality of values based on the first frequency and the first amplitude. The adaptive CDR loop dynamic control circuit is further to detect second sinusoidal jitter at a second frequency and a second amplitude and update the parameters of the CDR circuit to a second plurality of values based on the second frequency and the second amplitude. The first sinusoidal jitter is in a first incoming data signal and the second sinusoidal jitter is in a second incoming data signal.

A serial data receiver circuit included in a computer system may include both an analog and an ADC-based receiver circuit. A front-end circuit generates different equalized signals based on received signals that encode a serial data stream that includes multiple data symbols. During startup of a communication channel, phase information generated by the analog receiver circuit may be used to generate clock signals for the ADC-based receiver circuit. After a period of time, the ADC-based receiver circuit can generate its own phase information to be used in the generation of the clock signals.

The present invention is directed to data communication. More specifically, embodiments of the present invention provide a transceiver that processes an incoming data stream and generates a recovered clock signal based on the incoming data stream. The transceiver includes a voltage gain amplifier that also performs equalization and provides a driving signal to track and hold circuits that hold the incoming data stream, which is stored by shift and holder buffer circuits. Analog to digital conversion is then performed on the buffer data by a plurality of ADC circuits. Various DSP functions are then performed over the converted data. The converted data are then encoded and transmitted in a PAM format. There are other embodiments as well.