H04L7/0066

Method for symbol clock recovery in pulse position modulation (PPM) systems

A symbol clock recovery circuit for recovering a symbol clock in an M-ary pulse position modulation (PPM) signal. The recovery circuit includes a largest magnitude comparison circuit that selects a largest magnitude signal value from a group of M signal values aligned with a hypothesis symbol boundary location and the average of that largest magnitude value is compared with a threshold, or with results from other boundary location hypotheses, or with both, to determine the true position of the symbol boundary.

RECEIVEING DEVICE

A receiving device 20 includes a voltage controlled oscillator 22, a sampling unit 23, a control voltage generating unit 24, an error detecting unit 25, and a control voltage holding unit 26. The control voltage holding unit 26 holds a value of a control voltage Vc output from the control voltage generating unit 24. When the error detecting unit 25 detects an error of a digital signal, a control voltage held before error detection is provided to the voltage controlled oscillator 22.

Communication device, communication method, and communication program
12244345 · 2025-03-04 · ·

A communication device includes an interleaving unit that determines an interleaving length of transmit data to be transmitted through free-space optical communication, and interleaves the transmit data based on the determined interleaving length, and a shaping unit that shapes the interleaved transmit data so as to make the interleaving length detectable on a receiving side of the free-space optical communication.

SYSTEMS AND METHODS FOR SYNCHRONIZING WITH RADIO FREQUENCY SIGNALS
20260031970 · 2026-01-29 ·

Systems and methods for synchronizing with and decoding radio frequency signals are provided. In one aspect, a radio receiver includes an antenna configured to receive a radio frequency signal and digital signal processing circuitry configured to receive the radio frequency signal from the antenna and perform a first synchronization algorithm and a second synchronization algorithm on the radio frequency signal in parallel. The digital signal processing circuitry is further configured to determine which of the first synchronization algorithm and the second synchronization algorithm completes first and begin playback on the radio frequency signal based on synchronization with the radio frequency signal based on the determination of which of the first synchronization algorithm and the second synchronization algorithm completed first.