A multichannel receiver includes multiple receiver modules, each having: a voltage-controlled oscillator that generates a clock signal with a controllable frequency; a phase interpolator that applies a controllable phase shift to the clock signal to provide a sampling signal; a sampling element that produces a digital receive signal by sampling an analog receive signal in accordance with the sampling signal; a timing error estimator that operates on the digital receive signal to provide timing error estimates; a phase control filter that derives, from the timing error estimates, a phase control signal supplied to the phase interpolator, wherein the phase control signal minimizes a phase error between the sampling signal and the analog receive signal; and a frequency control filter that derives, from the timing error estimates, a frequency control signal for controlling the clock signal frequency, wherein the frequency control signal minimizes a frequency offset between the clock signal and the analog receive signal.

A symbol clock recovery circuit for recovering a symbol clock in an M-ary pulse position modulation (PPM) signal. The recovery circuit includes a largest magnitude comparison circuit that selects a largest magnitude signal value from a group of M signal values aligned with a hypothesis symbol boundary location and the average of that largest magnitude value is compared with a threshold, or with results from other boundary location hypotheses, or with both, to determine the true position of the symbol boundary.

A communication system has a host communication circuit and a client communication circuit, which are connected to each other by means of a single signal wire. The host communication circuit generates a voltage modulated signal on the signal wire based on a reference clock signal, which in each clock cycle has a first period with a significant voltage change based on a clock edge of the reference clock signal, and a second period with a basically constant voltage variation. The host communication circuit (HCC) further can demodulate a current modulated signal received via the signal wire from the client communication circuit. The client communication circuit is configured to detect the significant voltage change in order to generate respective sync pulses in a sync signal, which is used to generate a client clock signal. A current modulation is performed by the client communication circuit based on the data to be transmitted a predetermined settling time after one of the sync pulses until the respective following sync pulse.

A tracking method and apparatus of a communication system to prevent a timing difference and bit error rate performance degradation caused by unstable characteristics of a plurality of circuit devices are provided. The tracking method and apparatus include sampling signals received at receiving antennas, tracking sample values resulting from the sampling of the signals, and combining the tracked sample values.

A base station can cause a multitude of user devices in a network to be synchronized with the base station's clock using an ultra-lean low-complexity procedure in 5G or 6G. On a predetermined interval, the base station can transmit a timing signal in the guard-space of a predetermined resource element. The timing signal is a 180-degree phase reversal of the cyclic prefix centered in the guard-space. Each user device can receive the timing signal, determine how far the received timestamp point is from the middle of the guard-space (as viewed by the user device), and thereby determine a timing error between the user device clock and the base station clock, and correct the user device clock accordingly. In addition, the user device can average the timing adjustments over a number of instances, thereby determining a frequency offset if the average differs significantly from zero, and thereby adjust the clock frequency.

A clock recovery system for recovering an in-band communication clock in a wireless power transfer system can in include: a phase locked loop; and a bit decision block and a multiplexer that cooperate to selectively provide the error signal to the loop filter responsive to detected bits in the in-band communication bitstream. The phase locked loop can further include: a phase detector that computes an error signal from a difference between an instantaneous peak location and an estimated peak location correlated to a symbol in an in-band communication bitstream; a loop filter that selectively receives the error signal; and a voltage controlled oscillator that adjusts its output frequency responsive to an output of the loop filter.

A method and system eliminate echoes in the reproduction of radio signals transmitted via a radio channel. A radio signal transmitted by a transmitter is received by at least a first base station as a first audio signal and by at least a second base station as a second audio signal. The received audio signals are transmitted via an IP network to a control station for reproduction. The first and second audio signals arrive in the control station at different times or with a time shift and undergo a similarity analysis before their reproduction in the control station in order to reproduce the radio signal contained in both audio signals without echo if a similarity is established between the first audio signal and the second audio signal.