In order to provide a multiplexed clock generation apparatus in which synchronization between circuits based on a received clock is not lost, a clock generation apparatus is made to have a clock determination unit which determines whether a cycle shift time between a first clock signal and a second clock signal satisfies a predetermined condition or not and a clock switching unit which switches the first clock signal and the second clock signal based on determination of the clock determination unit. The clock determination unit determines that clock switching is possible when, as the predetermined condition, a first condition that a cycle shift time is equal to or more than a period from a setup start time to a hold end time of a signal specified for a clock bus and a second condition that the cycle shift time exists before the next setup start time are satisfied together.

A receiving device 20 includes a voltage controlled oscillator 22, a sampling unit 23, a control voltage generating unit 24, an error detecting unit 25, and a control voltage holding unit 26. The control voltage holding unit 26 holds a value of a control voltage Vc output from the control voltage generating unit 24. When the error detecting unit 25 detects an error of a digital signal, a control voltage held before error detection is provided to the voltage controlled oscillator 22.

Systems, methods and apparatus are described that facilitate transmission of data, particularly between two devices within an electronic apparatus. Two Integrated Circuit (IC) devices may be collocated in an electronic apparatus and communicatively coupled through a 3-wire, 3-phase interface. A data transfer method operational on a first of the two or more devices includes determining presence of a misalignment of the 3-wire communication link involving two or more wires, and inverting a first bit of a 3-bit symbol encoded in a transition of signaling state of the 3-wire communication link when the misalignment of the 3-wire communication link is determined to affect phase relationships between two or more signals carried on the three wires, such that inverting the first bit corrects the phase relationships between the two or more signals. A version of the 3-phase signal may be communicated in a different phase state through each of three wires.

The present invention is directed to data communication. More specifically, an embodiment of the present invention provides a technique for detecting loss of signal. An incoming data stream is sampled and a recovered clock signal is generated accordingly. An output clock signal of a higher frequency than the recovered clock signal is generated by a transmission PLL. The frequency of the recovered clock signal is compared to a divided frequency of the output clock signal. If a difference between the recovered clock signal and the output clock signal is greater than a threshold, a loss of signal indication is provided. There are other embodiments as well.

Systems, methods and apparatus are described that facilitate transmission of data, particularly between two devices within an electronic apparatus. Two Integrated Circuit (IC) devices may be collocated in an electronic apparatus and communicatively coupled through a 3-wire, 3-phase interface. A data transfer method operational on a first of the two or more devices includes determining presence of a misalignment of the 3-wire communication link involving two or more wires, and inverting a first bit of a 3-bit symbol encoded in a transition of signaling state of the 3-wire communication link when the misalignment of the 3-wire communication link is determined to affect phase relationships between two or more signals carried on the three wires, such that inverting the first bit corrects the phase relationships between the two or more signals. A version of the 3-phase signal may be communicated in a different phase state through each of three wires.

A signal reproduction circuit includes: an oscillator generating first clock and second clock having a same frequency but different phases; and a feedback circuit to control the oscillator in accordance with a phase relation and a frequency relation between input data and the first clock, wherein the feedback circuit includes: a frequency-phase detection circuit to compare a clock phase control signal and a clock phase detection signal and generate a frequency phase signal indicating the frequency relation between the input data and the first clock, a state detection circuit to detect a lock state in which falling edges or rising edges of the input data and the first clock synchronize and a frequency difference state in which frequencies of the input data and the first clock are different, and a selector to supply the frequency phase signal to the feedback loop only in the frequency difference state.

A clock and data recovery (CDR) circuit is provided. A phase detection circuit receives an input signal and a clock signal to output a first voltage signal. A first comparing circuit determines whether the first voltage signal is within a voltage range to output a first up signal and a first down signal. A counting circuit updates a counting value according to the input signal and the clock signal. A second comparing circuit determines whether the counting value is within a value range to output a second up signal and a second down signal. A selection circuit outputs a second voltage signal according to the first up signal, the first down signal, the second up signal, and the second down signal. A voltage controlled oscillator outputs the clock signal according to the first voltage signal and the second voltage signal.

An integrated circuit includes a plurality of receivers, each having a clock and data recovery circuit. A first local clock recovery circuit in a first receiver can be caused to produce a test clock which simulates a condition to be tested, and while a second receiver in the plurality of receivers that includes a second local clock recovery circuit is caused to use the test clock in place of the reference clock while receiving a test data sequence at its input. The clock and data recovery circuits in the receivers can include clock control loops responsive to loop control signals to modify the selected reference clock to generate the local clock in response to selective one of (i) a corresponding data signal for normal operation or during a test, and (ii) a test signal applied to the clock control loop in which case the test clock is produced.

A device includes receiver circuitry to receive incoming signals on a clock lane and data lanes and detection circuitry. The detection circuitry is to monitor the incoming signals on the clock lane, and determine that an incoming pattern of the incoming signals on the clock lane does not correspond to a clock pattern associated with communicating data on the data lanes. The detection circuitry is to initiate a power-down sequence in response to determining that the incoming pattern does not correspond to the clock pattern.

A device includes receiver circuitry to receive incoming signals on a clock lane and data lanes and detection circuitry. The detection circuitry is to monitor the incoming signals on the clock lane, and determine that an incoming pattern of the incoming signals on the clock lane does not correspond to a clock pattern associated with communicating data on the data lanes. The detection circuitry is to initiate a power-down sequence in response to determining that the incoming pattern does not correspond to the clock pattern.