There are provided examples of receivers, controller units and related methods, wherein one receiver includes: an adjustable sample provider configured to provide samples of an input signal using an adjustable sample timing; a feedback path configured to provide a feedback signal to the adjustable sample provider on the basis of a timing error, wherein the feedback path includes a loop filter configured to provide sample timing information to the adjustable sample provider; and a replacement value provider configured to provide a replacement sample timing information replacing the sample timing information provided by the feedback path when an input signal does not fulfil a predetermined requirement for a feedback-based sample timing adaptation, wherein the replacement value provider is configured to provide the replacement sample timing information considering a timing error information, or a quantity derived from the timing error information, over a longer time period when compared to a time period considered by the loop filter for a provision of the sample timing information.

The present disclosure provides a signal receiving apparatus having anti-RFI mechanism that includes an ADC circuit, an equalization circuit and a clock recovery circuit. The ADC circuit performs conversion of an input analog signal according to an internal clock signal, to generate an input digital signal. The equalization circuit equalizes the input digital signal such that the clock recovery circuit adjusts a phase of the internal clock signal and extracts a frequency by performing statistics on phase deviation amount information in a unit of a time window. The clock recovery circuit discards a corresponding phase deviation amount when a signal interference parameter of one of a sub time window is larger than a threshold value to update the phase deviation amount information, and generates an adjusting signal to adjust a frequency of the internal clock signal accordingly.

A communication receiving device includes a clock data recovery circuit, an analog-to-digital converter (ADC), a channel evaluating circuit, a first equalizer, and a selector. The clock data recovery circuit is configured to generate a clock signal according to a first digital signal. The ADC is coupled to the clock data recovery circuit, and configured to convert a first analog signal to a second digital signal according to the clock signal. The channel evaluating circuit is configured to analyze the second digital signal to output a selection signal. The first equalizer is coupled to the ADC, and configured to equalize the second digital signal to generate a third digital signal. The selector is coupled between the first equalizer, the ADC, and the clock data recovery circuit. The selector is configured to output the second digital signal or the third digital signal as the first digital signal according to the selection signal.

Apparatuses and methods of widespread equispatiated phase generation of a clock divided by a non-integer factor are described. One integrated circuit includes a clock divider and a phase generator. The clock divider receives a single-phase clock signal from a clock source and generates a divided clock signal. The phase generator receives the divided clock signal and the single-phase clock signal and generates multiple phase signals using the divided clock signal and the single-phase clock signal. The phase signals are equispatiated.

A transmission circuit includes a filter circuit configured to compensate for degradation of a multiplexed signal, based on a tap coefficient to be updated based on a first signal and a second signal which are time-division-multiplexed to the multiplexed signal, a phase locked loop (PLL) circuit configured to control, based on control information corresponding to phases of the first signal and the second signal, a frequency of a clock signal to be synchronized with the multiplexed signal whose degradation has been compensated, and a control circuit configured to generate, in response to an interruption of an input of the first signal or the second signal, the control information corresponding to the phase of the first signal or the second signal of which the interruption is not detected so as to output the control information to the PLL circuit.

A clock data recovery (CDR) mechanism qualifies symbols received from the data detector prior to using those symbols to compute a timing gradient. The disclosed CDR mechanism analyzes one or more recently received symbols to determine whether the current symbol should be used in computing the time gradient. When configured with a Mueller-Muller phase detector, the timing gradient for the received signal is set to zero if the current symbol is a 2 or a +2 and the previous symbol is non-zero. Otherwise, the Mueller-Muller timing gradient is evaluated in the traditional manner. When configured with a minimum mean-squared error phase detector, the timing gradient for the received signal is set to zero if the previous symbol is non-zero. Otherwise, the minimum mean-squared error timing gradient is evaluated in the traditional manner.

A transmission circuit includes a filter circuit configured to compensate for degradation of a multiplexed signal, based on a tap coefficient to be updated based on a first signal and a second signal which are time-division-multiplexed to the multiplexed signal, a phase locked loop (PLL) circuit configured to control, based on control information corresponding to phases of the first signal and the second signal, a frequency of a clock signal to be synchronized with the multiplexed signal whose degradation has been compensated, and a control circuit configured to generate, in response to an interruption of an input of the first signal or the second signal, the control information corresponding to the phase of the first signal or the second signal of which the interruption is not detected so as to output the control information to the PLL circuit.

A multi-lane transmitter and method of detecting a sync loss are provided. The method includes generating a high-speed clock signal and a sync reset signal synchronized to the high-speed clock signal. A sync loss pulse is generated based on the high-speed clock signal, and the sync loss pulse is provided to each of plural serializer circuits. Each serializer circuit generates a sampled sync loss signal by sampling the sync loss pulse in accordance with a parallel clock signal, and a Boolean value is assigned to the sampled sync loss signal and output. A logic block detects a sync loss when the sampled sync loss signal of any serializer circuit is out of sync from the sync loss pulse based on the Boolean value.

Techniques and apparatus for detection of a signal at an I/O interface module are described. In one embodiment, for example, an apparatus to provide signal detection may include at least one receiver, at least one memory, and logic for a signal detection module, at least a portion of the logic comprised in hardware coupled to the at least one memory and the at least one receiver, the logic to access a plurality of pulse signals of a clock and data recovery (CDR) circuit, analyze at least one pulse characteristic of the plurality of pulse signals, and generate a signal determination to indicate a signal at the at least one receiver based on the at least one pulse characteristic. Other embodiments are described and claimed.

There are provided examples of receivers, controller units and related methods, wherein one receiver includes: an adjustable sample provider configured to provide samples of an input signal using an adjustable sample timing; a feedback path configured to provide a feedback signal to the adjustable sample provider on the basis of a timing error, wherein the feedback path includes a loop filter configured to provide sample timing information to the adjustable sample provider; and a replacement value provider configured to provide a replacement sample timing information replacing the sample timing information provided by the feedback path when an input signal does not fulfil a predetermined requirement for a feedback-based sample timing adaptation, wherein the replacement value provider is configured to provide the replacement sample timing information considering a timing error information, or a quantity derived from the timing error information, over a longer time period when compared to a time period considered by the loop filter for a provision of the sample timing information.