A device includes receiver circuitry to receive incoming signals on a clock lane and data lanes and detection circuitry. The detection circuitry is to monitor the incoming signals on the clock lane, and determine that an incoming pattern of the incoming signals on the clock lane does not correspond to a clock pattern associated with communicating data on the data lanes. The detection circuitry is to initiate a power-down sequence in response to determining that the incoming pattern does not correspond to the clock pattern.

A method for transmitting real-time messages in a computer network (100), in particular real-time computer network, wherein said network comprises two or more computing nodes (21, 22, 23, 24, 25, 26) and one or more star couplers (1, 2, 3, 4), wherein said nodes are interconnected via at least one star coupler, wherein each node is connected to at least one star coupler via at least one of the communication links (50), and wherein the nodes exchange messages (M1, M2) with one another and with the at least one star coupler, and wherein star couplers, which are synchronized to a global time base (C), transmit a first non-empty set (SSET) of real-time messages according to a synchronized communication paradigm, and/or wherein computing nodes, which are synchronized to the global time base, transmit said first non-empty set of real-time messages according to the synchronized communication paradigm, wherein a star coupler, which is not synchronized to a global time base, and/or a computing node, which is not synchronized to a global time base, transmits a second non-empty subset (CSET) of said first non-empty subset of real-time messages according to an unsynchronized communication paradigm and stops the transmission of said second non-empty subset of real-time messages according to the synchronized communication paradigm.

According to one embodiment, a base station apparatus includes: a radio equipment control that generates a baseband signal including data; a microwave apparatus that modulates the baseband signal to a microwave to transmit by radio; a microwave apparatus that demodulates the received first microwave to the baseband signal, then extracts a clock from a cycle of the data included in the baseband signal, imports the baseband signal in synchronization with the clock, and plays back the data; and a radio equipment that modulates the data played back by the microwave apparatus to a high-frequency signal, and the microwave apparatus outputs dummy data instead of the played back data when a frequency fluctuation amount of the clock exceeds a predetermined range.

Disclosed herein are systems and methods for clock sustain in a two-wire communication systems and applications thereof. In some embodiments, in a clock sustain state, slave nodes with processors and digital to analog converters (DACs) may be powered down efficiently in the event of lost bus communication. For example, when the bus loses communication and a reliable clock cannot be recovered by the slave node, the slave node may enter the sustain state and, if enabled, signals this event to a general purpose input/output (GPIO) pin. In the clock sustain state, the slave node phase lock loop (PLL) may continue to run for a predetermined number of SYNC periods, while attenuating the inter-integrated circuit transmit (I2S DTXn) data from its current value to 0. After the predetermined number of SYNC periods, the slave node may reset and reenter a power-up state.

A loss of lock detection circuit includes detection circuitry and pulse accumulation circuitry. The detection circuitry includes a first flip-flop, a second flip-flop, and a third flip-flop. The first flip-flop is configured to synchronize a data stream to a first edge of a clock signal. The second flip-flop is configured to synchronize the data stream to a second edge of the clock signal. The third flip-flop is clocked by the data stream, and is configured to store a combined output of the first flip-flop and the second flip-flop at an edge of the data stream. The pulse accumulation circuitry is coupled to the detection circuitry. The pulse accumulation circuitry is configured to collect pulses generated by the third flip-flop.

A sampling phase adjustment device and an adjusting method thereof are disclosed. Sampling phase adjustment device includes feedback summer, adaptive equalizer unit, clock and data recovery (CDR) circuit, data slicer, error slicer, sample calculator unit and enable circuit. The adjusting method is as follows: the data slicer and error slicer receive a sum value generated from the feedback summer, and generate a data signal and an error signal, respectively. The adaptive equalizer unit provides an equalizing signal to the feedback summer and a reference signal to the error slicer. The sample calculator unit generates a sampling adjustment signal based on the data signal and error signal. The CDR circuit is configured to output and adjust a clock signal based on the sampling adjustment signal and data signal. The enable circuit enables the adaptive equalizer unit and the sample calculator unit alternatively.

Embodiments herein relate to optoelectronic transceivers with power management. An optoelectronic device may include a photodetector, a loss of signal (LOS) detector coupled with the photodetector, and a re-timer coupled with the LOS detector, wherein a component of the re-timer is to be disabled in response to a detection by the LOS detector that an optical signal has not been received for a predetermined time period. In some embodiments, the LOS detector is coupled with a driver disable input of the re-timer and a driver component of the re-timer is to be disabled. In some embodiments, a clock data recovery circuit, a transmit module re-timer and modulator, and/or a laser may be disabled. In various embodiments, components may be re-enabled in response to detection that an optical signal is being received and/or an electrical signal is received for optical transmission. Other embodiments may be described and/or claimed.

Systems and methods are disclosed for detecting and compensating for timing excursions in a data channel. If a signal contains discontinuities in phase, a detector of the channel may lose lock on the signal, resulting in the channel incorrectly adjusting a sampling phase toward a following symbol or previous symbol. This is referred to as a cycle slip, where the integer alignment of the sampling of a signal contains a discontinuity over the duration of a sector, preventing decoding of the signal. A circuit may be configured to detect a cycle slip during processing of a signal at a data channel based on timing error values, and when the signal fails to decode, shift an expected sampling phase of a detector for a subsequent signal processing attempt. Shifting the expected sampling phase can cause the channel to adjust the sampling phase in the correct direction, thereby preventing a cycle slip.

Provided are systems and methods for a reliable precision time architecture in a network. In various implementations, the network can be configured with a first time synchronization tree, the first time synchronization tree providing a first network time to network devices in the network. Each network device can further synchronize to the first network time. The network can further be configured with a second time synchronization tree. The second time synchronization tree can provide a second network time to the network devices on the network. The network devices can also synchronize to the second network time. The network devices can further be configured to use the first network time as a current time.

A receiving device 20 includes a voltage controlled oscillator 22, a sampling unit 23, a control voltage generating unit 24, an error detecting unit 25, and a control voltage holding unit 26. The control voltage holding unit 26 holds a value of a control voltage Vc output from the control voltage generating unit 24. When the error detecting unit 25 detects an error of a digital signal, a control voltage held before error detection is provided to the voltage controlled oscillator 22.