A circuit includes a voltage-controlled oscillator (VCO) and a frequency divider. The frequency divider input is coupled to the VCO output. The circuit further includes a phase-frequency detector (PFD). A control output of the PFD is coupled to the VCO. A first PFD input is coupled to a first frequency divider output, and a second PFD input is coupled to a second frequency divider output. The first frequency divider output is configured to provide a first frequency divider signal and the second frequency divider output is configured to provide a second frequency divider signal 90 degrees out of phase with respect to the first frequency divider signal. The PFD is configured to detect an occurrence of at least two edges of a signal on the data input while the second frequency divider signal is continuously logic high across the at least two edges.

A method uses a distributed data acquisition system with multiple, physically unconnected, data acquisition units, that can be in wireless communication with a remote host, to timestamp measurement data with sub-microsecond time base accuracy of sampling clock relative to an absolute timeframe. A current absolute time is derived from messages received from a satellite radio beacon positioning system (GPS). Measurement data is sampled by each unit at a specified sampling rate. Using hardware logic, batches of sampled data are associated with corresponding timestamps representing the absolute time at which the data was sampled. Data and timestamps may be transmitted to the host. A time offset bias is compensated by comparing timestamps against a nominal time based on start time and nominal sampling rate. The sampling clock rate may be disciplined using time pulses from the GPS receiver. An initial start of data sampling by all units can also be synchronized.

A method of encoding input data includes identifying an input packet of the input data, the input packet including a plurality of input words, each of the input words including pre bits, groupID bits, and post bits, organizing the plurality of input words into a plurality of groups based on groupID bits of the plurality of input words, identifying a key group of the plurality of groups based on a number of input words in each of the plurality of groups, determining a key value based on the pre bits, the groupID bits, and the post bits of one of the plurality of input words corresponding to the key group, and generating a plurality of coded words based on the key value and the plurality of input words.

An input signal arranged in frames is received. The frames include a cyclic redundancy check (CRC) field including a number of bits having bit edges. A timing signal is generated to include adjustable duration waveforms at one of a first duration value and a second duration value. A CRC check determines the occurrence, over the duration, of a number of waveforms of the timing signal having their duration adjusted to one of the first duration value and the second duration value which corresponds to the number of bits. A check signal is produced having a pass/fail value. If pass, the duration of the waveforms in the timing signal is maintained adjusted to the one of the first duration value and the second duration value. If fail, the duration of the waveforms in the timing signal is re-adjusted to the other of the first duration value and the second duration value.

A method of encoding input data includes identifying an input packet of the input data, the input packet including a plurality of input words, each of the input words including pre bits, groupID bits, and post bits, organizing the plurality of input words into a plurality of groups based on groupID bits of the plurality of input words, identifying a key group of the plurality of groups based on a number of input words in each of the plurality of groups, determining a key value based on the pre bits, the groupID bits, and the post bits of one of the plurality of input words corresponding to the key group, and generating a plurality of coded words based on the key value and the plurality of input words.

Methods and systems are described for adjusting the sample timing of a data sampler operating in a data signal processing path having a decision threshold associated with a decision feedback equalization (DFE) correction factor. The vertical threshold and sample timing of a spare sampler are varied to measure a signal amplitude trajectory of a pattern-verified signal according to detection of the predetermined transitional data pattern, the locked sampling point then being adjusted based on the measured signal amplitude trajectory.

A PAM4 signal processor calibrates slicing thresholds to reduce bit error rate in a PAM4 clock data recovery circuit by determining a first target value of a first slicing level. The PAM4 signal processor is configured to retrieve the first target value of the first slicing level and sweeps a first reference voltage down from the upper voltage threshold. The PAM4 signal processor is further configured to detect a first filtered output associated with the first reference voltage and determines whether the first filtered output is higher than a target value. Responsive to determining that the first filtered output is higher than the target value, the PAM4 signal processor stores the first reference voltage value

A method and system that provides for execution of a first calibration sequence, such as upon initialization of a system, to establish an operation value, which utilizes an algorithm intended to be exhaustive, and executing a second calibration sequence from time to time, to measure drift in the parameter, and to update the operation value in response to the measured drift. The second calibration sequence utilizes less resources of the communication channel than does the first calibration sequence. In one embodiment, the first calibration sequence for measurement and convergence on the operation value utilizes long calibration patterns, such as codes that are greater than 30 bytes, or pseudorandom bit sequences having lengths of 2.sup.N−1 bits, where N is equal to or greater than 7, while the second calibration sequence utilizes short calibration patterns, such as fixed codes less than 16 bytes, and for example as short as 2 bytes long.

A received signal is enhanced by removing distortion components of a concurrently transmitted signal. A received signal is acquired in a receive frequency band concurrently with transmission of a transmit signal in a transmit frequency band. The received signal includes an intermodulation distortion component of the transmit signal. A representation of the transmit signal is processed using a non-linear predictor to output a distortion signal representing predicted distortion components in the received signal. The received signal is enhanced using the distortion signal by removing the predicted distortion components from the received signal corresponding to the distortion signal.

Methods and systems are described for adjusting the sample timing of a data sampler operating in a data signal processing path having a decision threshold associated with a decision feedback equalization (DFE) correction factor. The vertical threshold and sample timing of a spare sampler are varied to measure a signal amplitude trajectory of a pattern-verified signal according to detection of the predetermined transitional data pattern, the locked sampling point then being adjusted based on the measured signal amplitude trajectory.