A method and a corresponding device for providing a delay value of a communication electronic unit. A digital input signal is delayed by a delay element. The input and the output signals of the delay element are sampled and the sampled signals are compared. A mismatch counter is incremented when the amplitudes of the sampled signals are not equal and a signal transition counter N is incremented when the input signal transitions. The provided delay value is proportional to the mismatch counting value, proportional to the length of the sampling intervals and inversely proportional to the signal transition counting value.

Methods and systems are described for generating a time-varying information signal at an output of a continuous time linear equalizer (CTLE), asynchronously sampling a data signal according to a sampling clock having a frequency less than a data rate of the data signal; generating corresponding pattern-verified samples for at least two data patterns, each of the at least two data patterns having a respective frequency content; determining corresponding frequency-specific voltage measurements associated with each of the at least two data patterns based on the corresponding pattern-verified samples of the at least two data patterns; and adjusting an equalization of the data signal based on a comparison of the corresponding frequency-specific voltage measurements.

A method includes computing electrical phase of electrical metering devices including obtaining data indicating zero-crossing times at first and second metering devices. A time difference between the zero-crossing times may be determined. In a first example, the time difference may be based at least in part on calculations involving a first value of a first free-run timer on a first metering device, a second value of a second free-run timer on a second metering device, the time of reception of a packet, and a latency defined by a time taken for the packet to propagate through at least one layer of at least one of the first metering device and the second metering device. A phase difference between the first zero-crossing and the second zero-crossing may be determined, based at least in part on the determined time difference.

A test and measurement instrument includes a first input port and a second input port that receive a first input signal modulated according to a first clock signal and a second input signal modulated according to a second clock signal, respectively. The first clock signal and the second clock signal may be asynchronous. The instrument also includes a phase reference that generates clock data for the second clock signal. The instrument includes a processor that determines time bases for the input signals that comprise different rates based on the received and/or generated clock data. The instrument also includes a display coupled to the processor. The display concurrently displays the first input signal in a first graticule according to the first time base and the second input signal in a second graticule according to the second time base.

Methods and systems are described for receiving a reference clock signal and a phase of a local oscillator signal at a dynamically-weighted XOR gate comprising a plurality of logic branches, generating a plurality of weighted segments of a phase-error signal, the plurality of weighted segments including positive weighted segments and negative weighted segments, each weighted segment of the phase-error signal having a respective weight applied by a corresponding logic branch of the plurality of logic branches, generating an aggregate control signal based on an aggregation of the weighted segments of the phase-error signal, and outputting the aggregate control signal as a current-mode output for controlling a local oscillator generating the phase of the local oscillator signal, the local oscillator configured to induce a phase offset into the local oscillator signal in response to the aggregate control signal.

A communication device includes a sampler configured to sample an input signal, wherein the sampler is configured to generate a sampled value for each sampling time of a sequence of sampling times, a sequence value generator configured to generate an output value for each sampling time of the sequence of sampling times based on the sampled values, wherein the sequence value generator is configured to set the output value for a sampling time based on the sampled value for the sampling time and based on a limitation of the difference between the output value for the sampling time and the output value for the preceding sampling time in the sequence of sampling times, and an edge detector configured to detect an edge in the input signal based on the output values.

A receiver and a detecting method thereof are provided. The receiver includes a plurality of antennas receiving a transmitted signal through multiple paths; and an equalizer collecting a plurality of sample signals by reflecting signals received in other antennas in the signals received in the plurality of antennas, and detecting a symbol of the transmitted signal by combining the plurality of sample signals that are collected with each other.

In one embodiment, an apparatus includes a clock channel to receive and distribute a clock signal to a plurality of data channels. At least some of the data channels may include: a first sampler to sample data; a second sampler to sample the data; and a deskew calibration circuit to receive first sampled data from the first sampler and second sampled data from the second sampler and generate a local calibration signal for use in the corresponding data channel. The apparatus may further include a global deskew calibration circuit to receive the clock signal from the clock channel, receive the first sampled data and the second sampled data from the plurality of data channels, and generate a global calibration signal for provision to the plurality of data channels. Other embodiments are described and claimed.

Methods and systems are described for generating two comparator outputs by comparing a received signal to a first threshold and a second threshold according to a sampling clock, the first and second thresholds determined by an estimated amount of inter-symbol interference on a multi-wire bus, selecting one of the two comparator outputs as a data decision, the selection based on at least one prior data decision, and selecting one of the two comparator outputs as a phase-error decision, the phase error decision selected in response to identification of a predetermined data decision pattern.

A channel between quantum controller modules (e.g., pulse processors) is operable to communicate high speed data required for processing qubit states that may be distributed across a quantum computer. The latency of the communication channel is deterministic and controllable according to a system clock domain.