Methods and systems are described for receiving a reference clock signal and a phase of a local oscillator signal at a dynamically-weighted XOR gate comprising a plurality of logic branches, generating a plurality of weighted segments of a phase-error signal, the plurality of weighted segments including positive weighted segments and negative weighted segments, each weighted segment of the phase-error signal having a respective weight applied by a corresponding logic branch of the plurality of logic branches, generating an aggregate control signal based on an aggregation of the weighted segments of the phase-error signal, and outputting the aggregate control signal as a current-mode output for controlling a local oscillator generating the phase of the local oscillator signal, the local oscillator configured to induce a phase offset into the local oscillator signal in response to the aggregate control signal.

A communication device includes an AFE configured to track and hold a first driving signal to produce a plurality of sample signals, a shift and hold module configured to store the plurality of sample signals, and an ADC configured to respectively convert the plurality of sample signals to a plurality of digitized sample signals, the ADC including a plurality of ADC slices. A DSP is configured to calibrate the AFE based on the plurality of ADC slices corresponding to the plurality of digitized sample signals and generate an output data stream comprising the plurality of digitized samples. A skew management module is configured to detect a skew of the plurality of digitized sample signals in the output data stream generated by the DSP module, generate a programmable skew offset based on the detected skew, and correct the skew in the output data stream based on the programmable skew offset.

System, methods and apparatus are described that facilitate communication of data over a multi-wire data communications link, particularly between two devices within an electronic apparatus. A receiving device receives a sequence of symbols over a multi-wire link. The receiving device further receives a clock signal via a dedicated clock line, wherein the dedicated clock line is separate from, and in parallel with, the multi-wire link. The receiving device decodes the sequence of symbols using the clock signal. In an aspect, a second clock signal is embedded in guaranteed transitions between pairs of consecutive symbols in the sequence of symbols. Accordingly, the receiving device decodes the sequence of symbols using the clock signal received via the dedicated clock line while ignoring the second clock signal.

An example burst mode clock data recovery circuit may include a clock recovery circuit coupled to receive a plurality of data signals, and provide a recovered clock signal in response. Each of the plurality of data signals includes data and an embedded clock signal, and the plurality of data signals may be based on an encoded symbol. The clock recovery circuit is coupled to generate the recovered clock signal in response to a first one of the plurality of data signals. A data recovery circuit may be coupled to receive the plurality of data signals and the recovered clock signal, and provide a plurality of recovered data signals in response to the recovered clock signal. The data recover circuit is coupled to delay each of the plurality of data signals, and capture each of the delayed plurality of data signals in response to the at least one clock pulse.

On the basis of the peak point of the integrated waveform of the reception signal for each one-bit time, a timing of resetting the integrated value of the reception signal for each one-bit time and a timing of determining whether a voltage of the reception signal for each one-bit time is high or low are indicated.

A semiconductor integrated circuit according to an embodiment includes an A/D converter, first and second equalizer circuits, and first and second controllers. The first equalizer circuit includes a first tap. The first and second equalizer circuits receive a signal based on a digital signal, and output first and second signals, respectively. The first controller adjusts a phase of a clock signal based on the first signal. The second controller an operation of adjusting a control parameter including a tap coefficient. In the operation, the second controller adjusts a tap coefficient of each of taps of the second equalizer circuit, and adjusts a tap coefficient of the first tap based on an adjustment result of each tap coefficient of the second equalizer circuit.

Embodiments of this disclosure provide an apparatus and method for generating a transmitting sequence, a training sequence synchronization apparatus and method, an apparatus and method for estimating channel spacing and a system. The training sequence synchronization apparatus includes: a delay correlation processing unit configured to parallelly perform autocorrelation operations of different delay amounts on a receiving sequence containing a periodic training sequence to obtain multiple parallel correlation sequences; a superimposition processing unit configured to perform a superimposition operation on the multiple parallel correlation sequences to obtain a synchronization correlation sequence; and a synchronization extracting unit configured to perform a synchronization position extraction on the synchronization correlation sequence to obtain a synchronization position of the training sequence. With the embodiments of this disclosure, anti-noise performance of the training sequence may be enhanced.

Nyquist folding receivers (NYFRs) are disclosed that use three or more non-modulated sampling clock signals with different frequencies to produce multiple projections in a sampled output. Using these three or more different sampling clock signals, multiple Nyquist zones are aliased together while still allowing signals from different Nyquist zones to be separated and identified in later processing based upon the sampling provided by the different sampling clock signals. NYFR sampling receivers are also disclosed that simultaneously produce multiple separate and different parallel channels from an input signal, with each different channel having a different sampling clock sampling rate from the other channels so as to generate a respective folding pattern that is different from the folding pattern generated by the respective RF sampling rate of each of the other simultaneous and parallel channels. A particular signal may be separated and identified by matching it to the respective different folding patterns in each of the simultaneous multiple different parallel channels.

The present invention discloses a time domain pilot design solution suitable for a single-carrier MIMO system. The design solution comprises a time domain pilot location design and a training sequence design. In the present invention, several identical ZCZ sequences are uniformly inserted into each of the data blocks in the same data stream to serve as training sequences, wherein the training sequences inserted into different data streams are different. In addition, the present invention also discloses a simple algorithm for pilot tracking and phase correction suitable for the time domain pilot design solution for the single-carrier MIMO system. The time domain pilot design solution for a single-carrier MIMO system and the algorithm for pilot tracking and phase correction as disclosed in the present invention can improve the performance of a system.

A method comprises receiving an input signal at an input of a receiver and retrieving a data sample signal and an error sample signal from the input signal. The method also comprises applying an adaptive procedure to generate a feedback code using the data sample signal and the error sample signal for feeding back into a decision feedback equalization (DFE) module. Further, it comprises converting the feedback code into a corresponding voltage value and assigning the corresponding voltage value as a tap weight for the DFE module. Finally, it comprises generating an edge sample signal by applying DFE to the input signal using the DFE module, wherein the DFE is based on the tap weight.