A system for communicating data over a transmission line is disclosed. In one example implementation, the system may include a transmitter configured to modulate a control signal onto an RF signal using amplitude-shift keying modulation to generate a transmit signal. The system may include a receiver and a transmission line coupling the transmitter to the receiver. The transmitter may be configured to transmit the transmit signal over the transmission line to the receiver, and the receiver may be configured to de-modulate the control signal and extract clock information associated with the transmitter. In some embodiments, the system may include a tuning circuit and a modal antenna, and the tuning circuit may be or include the receiver. The receiver may be configured to adjust a mode of the modal antenna based on the control signal transmitted by the transmitter.

Embodiments of the present invention synchronize multiple synthesizers, such as phase-locked loops (PLLs), in a manner that does not require communication or coordination between the synthesizers. Specifically, each synthesizer is part of a synthesizer circuit that includes a synthesizer (e.g., a PLL), a phase measurement circuit, and a synchronization circuit. A common reference signal (e.g., an alternating clock signal) is provided to the synthesizer circuits. In one exemplary embodiment, in each synthesizer circuit, the phase measurement circuit measures a phase difference between the reference signal and a corresponding output of the synthesizer, and the synchronization circuit adjusts the synthesizer operation based on the measured phase difference in such a way that all of the synthesizers operate in-phase with one another relative to the common reference signal, without having any communication or coordination between the two synthesizer circuits other than provision of the common reference signal.

Improved serial communication is provided in a system where each node regenerates data and transmits it to at least one other node in the system. Pulse width modulation (PWM) is used to encode the data. Preferably, all pulse shapes of the PWM start with a synchronization feature. It is also preferred that the regeneration delay in each node be less than the system clock period.

Improved serial communication is provided in a system where each node regenerates data and transmits it to at least one other node in the system. Pulse width modulation (PWM) is used to encode the data. Preferably, all pulse shapes of the PWM start with a synchronization feature. It is also preferred that the regeneration delay in each node be less than the system clock period.

In a transmission circuit, a first pulse signal with a first frequency and a second pulse signal with a second frequency are output according to a rising edge and a falling edge of a first input signal, respectively. When a second input signal indicates an active level, the second pulse signal is output according to the falling edge of the first input signal and the second frequency is changed to a third frequency. In a reception circuit, a first level of a first output signal is changed to a second level according to a first induced signal via a transformer, the second level of the first output signal is changed to the first level according to a second induced signal via the transformer, and a second output signal is changed to an active level when a frequency of the second induced signal has changed to the third frequency.

In a transmission circuit, a first pulse signal with a first frequency and a second pulse signal with a second frequency are output according to a rising edge and a falling edge of a first input signal, respectively. When a second input signal indicates an active level, the second pulse signal is output according to the falling edge of the first input signal and the second frequency is changed to a third frequency. In a reception circuit, a first level of a first output signal is changed to a second level according to a first induced signal via a transformer, the second level of the first output signal is changed to the first level according to a second induced signal via the transformer, and a second output signal is changed to an active level when a frequency of the second induced signal has changed to the third frequency.

Disclosed clock recovery modules provide improved performance with only limited complexity and power requirements. In one illustrative embodiment, a clock recovery method includes: oversampling a receive signal to obtain mid-symbol interval (MSI) samples and between-symbol interval (BSI) samples; processing at least the MSI samples to obtain symbol decisions; filtering the symbol decisions to obtain BSI targets; determining a timing error based on a difference between the BSI samples and the BSI targets; and deriving from the timing error a clock signal for said oversampling.

Disclosed clock recovery modules provide improved performance with only limited complexity and power requirements. In one illustrative embodiment, a clock recovery method includes: oversampling a receive signal to obtain mid-symbol interval (MSI) samples and between-symbol interval (BSI) samples; processing at least the MSI samples to obtain symbol decisions; filtering the symbol decisions to obtain BSI targets; determining a timing error based on a difference between the BSI samples and the BSI targets; and deriving from the timing error a clock signal for said oversampling.

According to an embodiment, a receiver is described comprising an input configured to receive a digital input signal and a digital filter configured to deliver a filtered digital output signal and to deliver stability information wherein the digital filter is configured to enter or stay in a transition state after a transition at the input signal, leave the transition state when the input signal is considered being stable, update the output signal when leaving the transition state and deliver the stability information indicating transitions at the input signal during transition state.

According to an embodiment, a receiver is described comprising an input configured to receive a digital input signal and a digital filter configured to deliver a filtered digital output signal and to deliver stability information wherein the digital filter is configured to enter or stay in a transition state after a transition at the input signal, leave the transition state when the input signal is considered being stable, update the output signal when leaving the transition state and deliver the stability information indicating transitions at the input signal during transition state.