Managing clock-data recovery for a modulated signal from a communication channel comprises: receiving the modulated signal and providing one or more analog signals, providing one or more digital input streams from samples of the analog signals, and processing the digital input streams to provide decoded digital data. The processing comprises: determining the decoded digital data based on information modulated over a plurality of frequency elements associated with the modulated signal, based at least in part on transforms of the digital input streams; a clock signal based on clock recovery from the digital input streams; and determining a clock phase error estimate associated with the determined clock signal based at least in part on a sum that includes different weights multiplied by different respective summands corresponding to different sets of frequency elements.

A signaling system is described. The signaling system comprises a transmit device, a receive device including a partial response receive circuit, and a signaling path coupling the transmit device and the receive device. The receive device observes an equalized signal from the signaling path, and includes circuitry to use feedback from the most recent previously resolved symbol to sample a currently incoming symbol. The transmit device equalizes transmit data to transmit the equalized signal, by applying weighting based on one or more data values not associated with the most recent previously resolved symbol value.

According to an embodiment, a receiver is described comprising an input configured to receive a digital input signal and a digital filter configured to deliver a filtered digital output signal and to deliver stability information wherein the digital filter is configured to enter or stay in a transition state after a transition at the input signal, leave the transition state when the input signal is considered being stable, update the output signal when leaving the transition state and deliver the stability information indicating transitions at the input signal during transition state.

According to an embodiment, a receiver is described comprising an input configured to receive a digital input signal and a digital filter configured to deliver a filtered digital output signal and to deliver stability information wherein the digital filter is configured to enter or stay in a transition state after a transition at the input signal, leave the transition state when the input signal is considered being stable, update the output signal when leaving the transition state and deliver the stability information indicating transitions at the input signal during transition state.

Systems and methods for blind detection of a numerology of a received signal are described. In one aspect, a method is provided for a user equipment (UE) to blindly detect the numerology of a received signal. The method includes correlating cyclic prefix (CP) signals in the received signal in the time domain based on a plurality of hypotheses of subcarrier spacing (SCS) and determining a numerology of the received signal for a corresponding hypothesis of SCS of the plurality of hypotheses based on the correlated CP signals.

Embodiments of the present invention synchronize multiple synthesizers, such as phase-locked loops (PLLs), in a manner that does not require communication or coordination between the synthesizers. Specifically, each synthesizer is part of a synthesizer circuit that includes a synthesizer (e.g., a PLL), a phase measurement circuit, and a synchronization circuit. A common reference signal (e.g., an alternating clock signal) is provided to the synthesizer circuits. In one exemplary embodiment, in each synthesizer circuit, the phase measurement circuit measures a phase difference between the reference signal and a corresponding output of the synthesizer, and the synchronization circuit adjusts the synthesizer operation based on the measured phase difference in such a way that all of the synthesizers operate in-phase with one another relative to the common reference signal, without having any communication or coordination between the two synthesizer circuits other than provision of the common reference signal.

A receiver may include a plurality of receiving units connected with corresponding channels, and a clock data recovery unit connected with a sensing channel among the channels via a sensing line and connected with the receiving units via a common clock line. The receiving units may receive training pattern signals having the same transition direction through the channels in a training mode, and, in the training mode the clock data recovery unit may generate a phase-adjusted sampling clock signal so that a sampling time corresponds to a transition time of a training pattern signal of the sensing channel.

A receiver may include a plurality of receiving units connected with corresponding channels, and a clock data recovery unit connected with a sensing channel among the channels via a sensing line and connected with the receiving units via a common clock line. The receiving units may receive training pattern signals having the same transition direction through the channels in a training mode, and, in the training mode the clock data recovery unit may generate a phase-adjusted sampling clock signal so that a sampling time corresponds to a transition time of a training pattern signal of the sensing channel.

Techniques and circuits are proposed to increase averaging in the clock recovery band based on an amount of channel overlap in receivers using excess bandwidth for clock recovery, to mitigate the impact of spectral energy leaking into an active channel of interest from an adjacent active channel and to improve the accuracy of the phase estimate of the received transmitted clock.

Provided is a transmission device including: a transmission circuit that operates, on the basis of a mode signal indicating a first operation mode corresponding to a data transmission period or a second operation mode corresponding to a data transmission pause period, in the first operation mode or the second operation mode, and transmits data in which a clock signal is embedded; and a power supply noise reduction circuit that reduces noise of a power supply that supplies power to the transmission circuit when switching is performed between the first operation mode and the second operation mode.