A clock and data recovery circuit includes a voltage controlled oscillator, a frequency detector and a control circuit. The voltage controlled oscillator is configured to generate a clock signal according to a voltage signal. The frequency detector is configured to detect whether increasing a frequency of the clock signal is required according to a plurality of sampling results of the input data signal and accordingly generate a first up control signal. The control circuit is coupled to the voltage controlled oscillator and the frequency detector and configured to adjust the voltage signal according to the first up control signal. The clock and data recovery circuit operates in a data recovery mode after detecting that the frequency of the clock signal is locked, and the frequency detector is configured to detect whether increasing the frequency of the clock signal is required in the data recovery mode.

Provided are a communication device, an industrial machine, and a communication method that contribute to accurate evaluation of communication quality. The present invention comprises: a reception unit that receives a serial signal; and a signal string acquisition unit that samples the serial signal at second periods that are shorter than a first period, which is a 1-bit period of the serial signal, thereby acquiring a signal string corresponding to 1 bit of the serial signal.

Provided are a communication device, an industrial machine, and a communication method that contribute to accurate evaluation of communication quality. The present invention comprises: a reception unit that receives a serial signal; and a signal string acquisition unit that samples the serial signal at second periods that are shorter than a first period, which is a 1-bit period of the serial signal, thereby acquiring a signal string corresponding to 1 bit of the serial signal.

A transmitter includes a modulator configured to digitally generate a communication signal whose modulation represents coded information to be transmitted to a local management unit. The transmitter can include a control unit configured to generate harmonic frequencies that are in-phase, inverted, or out-of-phase from a raw signal using fundamental frequencies for modulation.

A transmitter includes a modulator configured to digitally generate a communication signal whose modulation represents coded information to be transmitted to a local management unit. The transmitter can include a control unit configured to generate harmonic frequencies that are in-phase, inverted, or out-of-phase from a raw signal using fundamental frequencies for modulation.

Disclosed are some examples of retimer circuitry, systems and methods. In some implementations, clock data recovery circuitry is coupled between a receiver and a transmitter. The clock data recovery circuitry is configured to: extract a data component from an input data signal associated with the receiver, provide the data component to the transmitter, and generate a phase control signal. Phase interpolator circuitry is coupled with the clock data recovery circuitry. The phase interpolator circuitry includes a phase interpolator configured to: receive the phase control signal, generate, based on the phase control signal, an output clock signal, and provide the output clock signal to the transmitter to track data packets of the data component.

Disclosed are some examples of retimer circuitry, systems and methods. In some implementations, clock data recovery circuitry is coupled between a receiver and a transmitter. The clock data recovery circuitry is configured to: extract a data component from an input data signal associated with the receiver, provide the data component to the transmitter, and generate a phase control signal. Phase interpolator circuitry is coupled with the clock data recovery circuitry. The phase interpolator circuitry includes a phase interpolator configured to: receive the phase control signal, generate, based on the phase control signal, an output clock signal, and provide the output clock signal to the transmitter to track data packets of the data component.

An apparatus for generating a data signal comprises a processing circuit configured to generate the data signal, the data signal comprising a sequence of a first signal edge of a first type, a second signal edge of a second type, and a third signal edge of the first type, the first signal edge and the second signal edge being separated by a first time period corresponding to first data to be transmitted, and the second signal edge and the third signal edge being separated by a second time period corresponding to second data to be transmitted. An output interface circuit is configured to output the data signal.

The present application discloses a network card, time synchronization methods and devices, and computer storage media. The network card includes: a crystal oscillator configured to generate a clock pulse signal; a phase-locked loop configured to provide a local clock source for the network card according to the clock pulse signal; and a connector connected with a host. The network card transmits synchronized time information to each of N VMs, which are run on the host, through a shared channel, where N≥2.

The present application discloses a network card, time synchronization methods and devices, and computer storage media. The network card includes: a crystal oscillator configured to generate a clock pulse signal; a phase-locked loop configured to provide a local clock source for the network card according to the clock pulse signal; and a connector connected with a host. The network card transmits synchronized time information to each of N VMs, which are run on the host, through a shared channel, where N≥2.