Disclosed herein are related to systems and methods for correcting non-linearity due to duty cycle error. In one aspect, a system includes a mixer configured to up-convert transmission (Tx) data, a coefficient calibrator configured to select a target value of a coefficient based on a measurement of an interference signal due to non-linearity of the mixer, and an interference canceller coupled to the coefficient calibrator and the mixer. In some embodiments, the interference canceller is configured to generate compensated Tx data based on the Tx data and the selected target value of the coefficient and provide the compensated Tx data to the mixer. In some embodiments, the compensated Tx data corrects for the non-linearity of the mixer.

A physical layer transceiver and a network node including the transceiver. The transceiver includes a media independent interface, a converter circuit block comprising circuitry configured to convert digital signals to analog signals for transmission over a network communications medium and convert analog signals received over the medium to digital signals, and one or more processing blocks configured to process digital data communicated between the media independent interface and the converter circuit block according to a network protocol. Management and control circuitry including power management circuitry and reset circuitry are provided. The transceiver further includes at least one single event effect (SEE) monitor, such as an ambience monitor, a configuration register monitor, a state machine monitor, or a phase locked loop (PLL) lock monitor, configured to detect and respond to an SEE event in the transceiver.

A physical layer transceiver and a network node including the transceiver. The transceiver includes a media independent interface, a converter circuit block comprising circuitry configured to convert digital signals to analog signals for transmission over a network communications medium and convert analog signals received over the medium to digital signals, and one or more processing blocks configured to process digital data communicated between the media independent interface and the converter circuit block according to a network protocol. Management and control circuitry including power management circuitry and reset circuitry are provided. The transceiver further includes at least one single event effect (SEE) monitor, such as an ambience monitor, a configuration register monitor, a state machine monitor, or a phase locked loop (PLL) lock monitor, configured to detect and respond to an SEE event in the transceiver.

A method for reception of a signal by a subscriber of a real-time network. The signal includes a signal clock having a signal clock frequency and the subscriber includes a counter, which has a counter clock with a counter clock frequency and which maps a local time of the subscriber. The method includes sampling the signal with a reception clock of a reception counter of the subscriber, the reception clock being derived from the counter clock, whereby the reception counter maps the local time of the subscriber, adapting a phase position of the reception clock to a phase position of the signal clock when said reception clock is derived from the counter clock, and sampling the signal at a reception clock frequency of the reception counter

Provided are a link capacity adjustment method and device. The method includes: a node device obtains a latency of a Physical Layer (PHY) for link capacity adjustment of a Flex Ethernet (FlexE) group; and clock offsets of all the PHYs in the FlexE group are aligned according to the obtained latency. According to embodiments of the present disclosure, the clock offsets of all the PHYs in the FlexE group are aligned, thereby preventing data loss caused by the clock offsets of the PHYs in the FlexE group during link capacity adjustment.

Provided are a clock synchronization method performed between communication nodes included in a communication network, the clock synchronization method comprises receiving a synchronization source signal through any one of remaining communication nodes except for an uppermost communication node included in the communication network, generating a reference clock for clock synchronization from the received synchronization source signal and transmitting the generated reference clock through a first path including at least a portion reverse to a second path through which a downlink signal is transmitted in the communication network.

Provided are a clock synchronization method performed between communication nodes included in a communication network, the clock synchronization method comprises receiving a synchronization source signal through any one of remaining communication nodes except for an uppermost communication node included in the communication network, generating a reference clock for clock synchronization from the received synchronization source signal and transmitting the generated reference clock through a first path including at least a portion reverse to a second path through which a downlink signal is transmitted in the communication network.

A single channel receiver includes an input terminal that receives an analog input signal, a mixer that down-mixes the analog input signal by use of a phase- and/or frequency-corrected oscillator frequency signal and shifts complex-valued information contained in the analog input signal to the real part (or alternatively to the imaginary part) to obtain an intermediate real-valued analog signal, an analog-to-digital-converter that converts the intermediate analog signal into an intermediate digital signal, a demodulator that demodulates the intermediate digital signal into a digital output signal, a phase tracking loop that detects zero-crossings in the intermediate digital signal to obtain phase error information representing a phase error in the intermediate digital signal, and an oscillator that generates the phase- and/or frequency-corrected oscillator frequency signal by compensating the phase and/or frequency error in the intermediate digital signal by correcting the phase of the oscillator frequency signal with the phase error information.

A clock data recovery circuit includes the following elements: a phase detector for outputting a phase adjustment signal by comparing a clock signal of a first node and an input signal; a charge pump for adjusting a charge amount of a second node according to the phase adjustment signal; a first switch including one end coupled to the second node and including another end coupled to a third node; a second switch including one end which receives a bias voltage and including another end coupled to the third node; a capacitor including a first electrode coupled to the third node; third switches; and voltage control oscillators including control terminals coupled to the third node and including output terminals coupled to the first node through the third switches.

A clock data recovery circuit includes the following elements: a phase detector for outputting a phase adjustment signal by comparing a clock signal of a first node and an input signal; a charge pump for adjusting a charge amount of a second node according to the phase adjustment signal; a first switch including one end coupled to the second node and including another end coupled to a third node; a second switch including one end which receives a bias voltage and including another end coupled to the third node; a capacitor including a first electrode coupled to the third node; third switches; and voltage control oscillators including control terminals coupled to the third node and including output terminals coupled to the first node through the third switches.