A clock data recovery circuit includes the following elements: a phase detector for outputting a phase adjustment signal by comparing a clock signal of a first node and an input signal; a charge pump for adjusting a charge amount of a second node according to the phase adjustment signal; a first switch including one end coupled to the second node and including another end coupled to a third node; a second switch including one end which receives a bias voltage and including another end coupled to the third node; a capacitor including a first electrode coupled to the third node; third switches; and voltage control oscillators including control terminals coupled to the third node and including output terminals coupled to the first node through the third switches.

High-speed communication links with self-aligned scrambling on a communication link that sends scrambled signals may include a slave device that may self-align by initially detecting an unscrambled preamble symbol and more particularly detect an edge of the unscrambled preamble symbol. Based on the detected edge, a fine alignment adjustment may be made by testing subsequent scrambled data for a repeated pattern such as an IDLE symbol by comparing the repeated pattern to a candidate scrambled sequence that has been received through the communication link. The comparison may use an exclusive OR (XOR) circuit on some bits to derive a scrambler seed that is used to test for a match for the remaining bits. If there is a match, the scrambler seed and frame alignment have been detected and alignment is achieved.

A transmission device included in one base station in a radio communication system including communication areas adjacent to each other in which the base station communicates with a plurality of wireless terminals includes: a modulation unit that generates a data symbol sequence; a synchronization signal generating unit that generates a first symbol sequence constituted by two or more continuous repetitions of reference sequence symbols being a reference, generates a second symbol sequence by performing frequency shifting on the first symbol sequence by using a phase rotation sequence so that the reference sequence symbols become orthogonal for each of the wireless terminals, and generates a synchronization signal; and a synchronization signal adding unit that generates a transmission signal by adding the synchronization signal to the data symbol sequence.

Systems and methods for asynchronous communication are disclosed. For example, a method for asynchronous communication includes encoding, by a transmitter circuit and according to a first clock signal, a bit sequence by converting a one-bit in the bit sequence into a first sequence and a zero-bit in the bit sequence into a second sequence. A length of the first sequence and a length of the second sequence differ by at least three bits. The method also includes communicating, by the transmitter circuit, the first sequence and the second sequence to a receiver circuit that decodes the first sequence and the second sequence according to a second clock signal that is independent of the first clock signal.

This invention provides an electronic apparatus which comprises a TIME-CODE terminal configured to output a time code signal which an external apparatus utilizes to perform synchronization related to a video, and a control unit configured to output a time code signal in which a bit in a predetermined field in the time code signal is set to a predetermined value, from the TIME-CODE terminal.

Methods, systems, and apparatus, including computer programs encoded on computer storage media, for encoding frameless packets. One of the methods includes receiving a data payload to be transmitted. The data payload is partitioned into multiple payload words, each payload word being of a predetermined size. A first sync word is added to each of the multiple payload words. A control word comprising label and an error checking value is added. A second sync word is added to the label and error checking word. If one or more counter criteria are satisfied while transmitting the multiple payload words, an idle word is transmitted before transmitting the label and error checking word.

A method of calibrating a high frequency signal measurement system is described. The measurement system is in the form of a network analyzer (6) and has first and second phase-locked signal sources (SS1 & SS2) and at least two measurement receivers (18a, 18b). A phase meter (26) is provided. A reference signal (F0) is outputted at a first frequency from the first signal source (SS1). The second signal source (SS2) steps through a multiplicity of different test frequencies (nF0), being phase-locked with the reference signal (F0), which are applied in turn to a part of the measurement system. Measurements are taken, via the two measurement receivers (18a, 18b), of characteristics of the resulting signal at a measurement plane. The absolute phase of the signal at the measurement plane is also measured with the phase meter (26). Calibration data is generated which relates the characteristics of the signals as measured by the measurement system (6) and the absolute phase as measured with the phase meter (26).

A method for synchronizing a data frame and data symbols in a communication system includes generating a training sequence including a serial sequence of data symbols that are conjugate symmetric, inserting the training sequence in a transmitter-side data frame, converting constituent data symbols of the transmitter-side data frame to communication signals, transmitting the communication signals from a transmitter to a receiver, converting the communication signals to a stream of received data symbols, detecting presence of the training sequence in the stream of received data symbols, and identifying a position of a received data frame from the presence of the training sequence.

In one embodiment, an apparatus includes a clock channel to receive and distribute a clock signal to a plurality of data channels. At least some of the data channels may include: a first sampler to sample data; a second sampler to sample the data; and a deskew calibration circuit to receive first sampled data from the first sampler and second sampled data from the second sampler and generate a local calibration signal for use in the corresponding data channel. The apparatus may further include a global deskew calibration circuit to receive the clock signal from the clock channel, receive the first sampled data and the second sampled data from the plurality of data channels, and generate a global calibration signal for provision to the plurality of data channels. Other embodiments are described and claimed.

A node synchronization method, includes: receiving a synchronization message by a first synchronization node in a network; determining whether to update a first local time of the first synchronization node according to the synchronization message by the first synchronization node; updating the first local time according to a synchronization time of the synchronization message by the first synchronization node when determining to update the first local time; and updating the synchronization time of the received synchronization message with the current first local time and forwarding the updated synchronization message by the first synchronization node.