Advanced detectors for vector signaling codes are disclosed which utilize multi-input comparators, generalized on-level slicing, reference generation based on maximum swing, and reference generation based on recent values. Vector signaling codes communicate information as groups of symbols which, when transmitted over multiple communications channels, may be received as mixed sets of symbols from different transmission groups due to propagation time variations between channels. Systems and methods are disclosed which compensate receivers and transmitters for these effects and/or utilize codes having increased immunity to such variations, and circuits are described that efficiently implement their component functions.

Communication systems and methods in accordance with various embodiments of the invention utilize modulation on zeros. Carrier frequency offsets (CFO) can result in an unknown rotation of all zeros of a received signal's z-transform. Therefore, a binary MOCZ scheme (BMOCZ) can be utilized in which the modulated binary data is encoded using a cycling register code (e.g. CPC or ACPC), enabling receivers to determine cyclic shifts in the BMOCZ symbol resulting from a CFO. Receivers in accordance with several embodiments of the invention include decoders capable of decoding information bits from received discrete-time baseband signals by: estimating a timing offset for the received signal; determining a plurality of zeros of a z-transform of the received symbol; identifying zeros from the plurality of zeros that encode received bits by correcting fractional rotations resulting from the CFO; and decoding information bits based upon the received bits using a cycling register code.

A master device communicates with a slave device through an asynchronous serial communications link. The master device includes a single pad configured to communicate a command frame including an address and a data frame including data with the slave device via a single wire; and a processing circuit configured to generate an oversampling clock signal from a clock signal, to perform a synchronization process for selecting one of a plurality of clock phases of the oversampling clock signal, and to perform a sampling process for sampling an each bit value included in the data frame transmitted from the slave device using a clock phase at the same position as the clock phase selected during the synchronization process.

Advanced modulation and demodulation schemes for LoRa or equivalent chirp spread spectrum transmissions, with differential modulation and symbol repetition improve the sensitivity in combination with soft demodulation methods.

Transmitter for chirp-modulated radio signals comprising a chirp generator configured to generate a series of chirp signals, wherein each chirp carries an element of information encoded as a cyclic shift, and has a phase encoding an error correction code dependent form the cyclic shift of the chirp, the transmitter further comprising a modulator configured to modulate the series of chirp onto a radio signal and a radio transmitter, transmitting the radio signal. receiver for chirp-modulated radio signals, comprising a clock unit and a demodulator configured for demodulating a series of received chirps signal, the demodulator having a dechirp unit, configured for determining a cyclic shift of each received chirp relative to a base chirp and an error correction code based on a phase of the received chirp, the receiver having a synchronism correction unit configured to detect and/or correct an error in the clock unit based on the error correction code.

Systems and methods for mapping a time-based data acquisition (DAQ) to an isochronous data transfer channel of a network. A buffer associated with the isochronous data transfer channel of the network may be configured. A clock and a local buffer may be configured. A functional unit may be configured to initiate continuous performance of the time-based DAQ, transfer data to the local buffer, initiate transfer of the data between the local buffer and the buffer at a configured start time, and repeat the transferring and initiating transfer in an iterative manner, thereby transferring data between the local buffer and the buffer. The buffer may be configured to communicate data over the isochronous data transfer channel of the network, thereby mapping the time-based DAQ to the isochronous data transfer channel of the network.

A sensor integrated circuit (IC) includes a sensing element configured to sense a parameter associated with a target, a processor coupled to the sensing element and configured to generate a sensed signal indicative of the parameter associated with the target, and an output module coupled to receive the sensed signal. The output module is configured to transmit absolute data on a message line at a first rate and transmit incremental data on one or more index lines at a second rate, wherein the second rate is faster than the first rate, wherein the incremental data comprises data associated with changes in the absolute data and wherein an edge or a pulse is used to indicate an incremental change has occurred in the absolute data.

A combined error checker and sequence generator which shares a LFSR is disclosed which reduces complexity, cost, and area required for implementation while also improving timing margin. A clock and data recovery system recovers a data signal received over a channel from a remote transceiver. Control logic selects different modes of operation of the system. An error detector compares the two sequence signals and records errors in response to differences between the two sequence signals. A sequence generator generates a sequence signal for use by the error detector as a reference sequence signal or for transmission to a remote transceiver. The system includes one or more switching elements configured to selectively route the generated sequence as feedback into the sequence generator or the received sequence signal into the sequence generator subject to whether the combined error checker and sequence generator is in error checker mode or sequence generator mode.

An input signal arranged in frames is received. The frames include a cyclic redundancy check (CRC) field including a number of bits having bit edges. A timing signal is generated to include adjustable duration waveforms at one of a first duration value and a second duration value. A CRC check determines the occurrence, over the duration, of a number of waveforms of the timing signal having their duration adjusted to one of the first duration value and the second duration value which corresponds to the number of bits. A check signal is produced having a pass/fail value. If pass, the duration of the waveforms in the timing signal is maintained adjusted to the one of the first duration value and the second duration value. If fail, the duration of the waveforms in the timing signal is re-adjusted to the other of the first duration value and the second duration value.

Communication systems and methods in accordance with various embodiments of the invention utilize modulation on zeros. Carrier frequency offsets (CFO) can result in an unknown rotation of all zeros of a received signal's z-transform. Therefore, a binary MOCZ scheme (BMOCZ) can be utilized in which the modulated binary data is encoded using a cycling register code (e.g. CPC or ACPC), enabling receivers to determine cyclic shifts in the BMOCZ symbol resulting from a CFO. Receivers in accordance with several embodiments of the invention include decoders capable of decoding information bits from received discrete-time baseband signals by: estimating a timing offset for the received signal; determining a plurality of zeros of a z-transform of the received symbol; identifying zeros from the plurality of zeros that encode received bits by correcting fractional rotations resulting from the CFO; and decoding information bits based upon the received bits using a cycling register code.