System and techniques for synchronizing a real-time clock and a network clock are described herein. A network device maintains an always running time (ART) replica of an ART in a compute system. The network device samples network time updates (e.g., precision time protocol messages) and the ART replica to produce error correction of the ART replica to the network time. The error correction is written to memory of the compute device to enable high precision synchronization between clock sources local to the compute device and the network time.

Advanced modulation and demodulation schemes for LoRa or equivalent chirp spread spectrum transmissions, with differential modulation and symbol repetition improve the sensitivity in combination with soft demodulation methods.

Managing clock-data recovery for a modulated signal from a communication channel comprises: receiving the modulated signal and providing one or more analog signals, providing one or more digital input streams from samples of the analog signals, and processing the digital input streams to provide decoded digital data. The processing comprises: determining the decoded digital data based on information modulated over a plurality of frequency elements associated with the modulated signal, based at least in part on transforms of the digital input streams; a clock signal based on clock recovery from the digital input streams; and determining a clock phase error estimate associated with the determined clock signal based at least in part on a sum that includes different weights multiplied by different respective summands corresponding to different sets of frequency elements.

An apparatus for providing fast-settling quadrature detection and correction includes: a quadrature correction circuit that receives four quadrature clock signals; a quadrature detector that selects two clock signals among the four quadrature clock signals; and a phase digitizer that generates a digital code indicating a phase difference between the two clock signals. The quadrature correction circuit adjusts a phase between the two clock signals using the digital code.

Systems and methods including a transmitter resource to transmit a message having one or more packets, each packet having a boundary identifier including a first placeholder generated based on or in response to data in a fixed-sized window of the message, and a second placeholder generated based on or in response to all data in a respective packet, and a receiver resource to receive the message and to detect the boundary identifiers of the respective packets.

Communication systems and methods in accordance with various embodiments of the invention utilize modulation on zeros. Carrier frequency offsets (CFO) can result in an unknown rotation of all zeros of a received signal's z-transform. Therefore, a binary MOCZ scheme (BMOCZ) can be utilized in which the modulated binary data is encoded using a cycling register code (e.g. CPC or ACPC), enabling receivers to determine cyclic shifts in the BMOCZ symbol resulting from a CFO. Receivers in accordance with several embodiments of the invention include decoders capable of decoding information bits from received discrete-time baseband signals by: estimating a timing offset for the received signal; determining a plurality of zeros of a z-transform of the received symbol; identifying zeros from the plurality of zeros that encode received bits by correcting fractional rotations resulting from the CFO; and decoding information bits based upon the received bits using a cycling register code.

A method and device for transmitting data reliably to at least one item of equipment is provided, wherein: from its initial clock H.sub.1, an item of equipment generates at least one first clock H.sub.1U from a rising edge of the initial clock H.sub.1 with a frequency F.sub.1U and a second clock H.sub.1D from a falling edge of the initial clock H.sub.1, with a frequency F.sub.1D, the item of equipment: reads the received data using at least one first rising edge of H.sub.1U and one falling edge consecutive to the first rising edge of H.sub.1U, then reads the received data using a first rising edge of H.sub.1D and a falling edge consecutive to the first rising edge of H.sub.1D, the four clock edges used being consecutive by 2F.sub.1, decodes at least the four messages using an error-correcting code, when at least one decoded message is correct, it uses the information contained in this message to drive a device linked to said item of equipment.

Devices and methods for calibrating communication lines are disclosed. A clock sets a frequency of transmission through a communication line. A delay compensator, comprising multi-tap delay lines introduces delays in a transmitted message to compensate for skew in the communication line. An error comparator, coupled to the delay compensator, identifies errors in the messages transmitted through the multi-tap delay lines above an error margin. A delay selector, coupled to the error comparator and to the delay compensator, selects taps of the multi-tap delay lines of the delay compensator. Taps of the multi-tap delay lines where no errors are identified for the selected clock frequency are stored in a memory.

The present disclosure relates to a circuit for calibrating a baud rate. The circuit includes: a first counter connected to a receiving module of a serial port chip and configured to record a first low level duration of a data frame received by the receiving module; a second counter configured to: receive a bit sampling pulse generated from sampling the data frame according to a current baud rate of the receiving module, and record a quantity of the bit sampling pulse in the first low level duration; a divider, connected to the first counter and the second counter and calculate a calibration baud rate according to the first low level duration and the quantity of the bit sampling pulse in the first low level duration; and a selector, connected to the receiving module and the divider and configured to output the calibration baud rate to the receiving module.

An apparatus for providing fast-settling quadrature detection and correction includes: a quadrature correction circuit that receives four quadrature clock signals; a quadrature detector that selects two clock signals among the four quadrature clock signals; and a phase digitizer that generates a digital code indicating a phase difference between the two clock signals. The quadrature correction circuit adjusts a phase between the two clock signals using the digital code.