A clock product includes a phase-locked loop configured to generate an output clock signal based on an input digital value and a feedback digital value. The input digital value corresponds to a first clock edge of a frequency-divided input clock signal and the feedback digital value corresponds to a second clock edge of a feedback clock signal. The clock product includes an input fractional divider configured to generate the input digital value based on an input clock signal, a divider value, and an input clock period digital code corresponding to a period of the input clock signal.

A clock product includes a phase-locked loop configured to generate an output clock signal based on an input digital value and a feedback digital value. The input digital value corresponds to a first clock edge of a frequency-divided input clock signal and the feedback digital value corresponds to a second clock edge of a feedback clock signal. The clock product includes an input fractional divider configured to generate the input digital value based on an input clock signal, a divider value, and an input clock period digital code corresponding to a period of the input clock signal.

A User Equipment and method for transmitting a random-access radio frequency (RF) signal by applying Asynchronous Coded Multiple Access (ACMA) in a communication system employing Orthogonal Frequency Division Multiplexing (OFDM) is described. The method including: encoding an information stream as OFDM symbols using a low rate Forward Error Correction (FEC) coding suitable for Successive Interference Cancellation (SIC) to form a payload; generating a burst, including symbols, by performing an inverse fast Fourier transform on a unique word (UW) multiplexed with the payload; and synchronizing a transmission of each of the symbols of the burst with consecutive symbol-start instants. The UW includes a plurality of Zadoff-Chu (ZC) like sequences disposed in a subset of consecutive symbol-start instants of the burst. A receiver detects burst arrival by searching for consecutive ZC-like sequences. Channel state estimation can be performed by using the UW with additional ZC-like sequences in the burst.

A method of frame synchronization comprises receiving a stream of bits, the stream comprising a sequence of frames, wherein each frame comprises a frame counter value representing the number of the frame in the sequence, and frame check bits for checking the validity of the frame counter value. The method comprises decoding a first section of bits, and trailing a first portion of the first section of bits as a trial counter value, and a second portion of the first section of bits as trial check bits. The method comprises checking if the trial counter value corresponds to a valid frame counter value using the trial check bits, and synchronizing based on whether the trial counter value is determined to correspond to a valid frame counter value.

Techniques and apparatus for detection of a signal at an I/O interface module are described. In one embodiment, for example, an apparatus to provide signal detection may include at least one receiver, at least one memory, and logic for a signal detection module, at least a portion of the logic comprised in hardware coupled to the at least one memory and the at least one receiver, the logic to access a plurality of pulse signals of a clock and data recovery (CDR) circuit, analyze at least one pulse characteristic of the plurality of pulse signals, and generate a signal determination to indicate a signal at the at least one receiver based on the at least one pulse characteristic. Other embodiments are described and claimed.

The present invention relates to a method for estimating a bit error probability using an error rate ratio of a frame synchronization word, to lower computational complexity such that the method can be implemented in a relatively simple and economical way at a high computational speed. The method includes the steps of: a) defining error rate ratios of frame synchronization words; b) setting a weighted least squares cost function with weights greater than or equal to 0 for the bit error probability using the error rate ratios of the frame synchronization words set in the step a); c) obtaining an estimated bit error probability value that minimizes the cost function set in the step b); and d) sequentially obtaining the weights so that a mean squared error of the estimated bit error probability value obtained in the step c) becomes small.

Disclosed in embodiments of this disclosure are a check code processing method, an electronic device and a storage medium. The check code processing method comprising: performing operations on m bits of the n.sup.th byte of a code block to obtain the n.sup.th bit of a first sequence; and performing operation on the first sequence of the code block with a same transmission period to obtain a check code.

A control method of an optical transceiver has an interrupt processing step of interrupting repetitive processing step in response to a command from a host apparatus and executing an interrupt process for transmitting monitoring data, and a step of setting the processing mode of the interrupt process to a first processing mode when one cycle of the repetitive processing step is shorter than a specific value, and setting the processing mode to a second processing mode when one cycle of the repetitive processing step is longer than the specific value. The interrupt process stores first data in the transmission register and stopping stretching of a clock signal, and reading out second data to be transmitted next from the memory unit. Furthermore, the interrupt process stops stretching of the clock signal after storing the first data in the transmission register and reading out the second data from the memory unit.

A primary device implementing the subject system of link establishment for single pair Ethernet may include at least one processor. The at least one processor may be configured to transmit a first synchronization sequence to a secondary device, detect a second synchronization sequence transmitted by the secondary device, the second synchronization sequence differing from the first synchronization sequence, and after detection of the second synchronization sequence, initiate a training stage, the train stage comprising exchanging training frames with the secondary device. The at least one processor may be further configured to enter a data mode for data transmissions after completion of the training stage, the data transmissions being distinct from the training frames. In the data mode, data may be forward error correction encoded and then scrambled.

Communication systems and methods in accordance with various embodiments of the invention utilize modulation on zeros. Carrier frequency offsets (CFO) can result in an unknown rotation of all zeros of a received signal's z-transform. Therefore, a binary MOCZ scheme (BMOCZ) can be utilized in which the modulated binary data is encoded using a cycling register code (e.g. CPC or ACPC), enabling receivers to determine cyclic shifts in the BMOCZ symbol resulting from a CFO. Receivers in accordance with several embodiments of the invention include decoders capable of decoding information bits from received discrete-time baseband signals by: estimating a timing offset for the received signal; determining a plurality of zeros of a z-transform of the received symbol; identifying zeros from the plurality of zeros that encode received bits by correcting fractional rotations resulting from the CFO; and decoding information bits based upon the received bits using a cycling register code.