A receiver is configured to receive a series of command signals and a series of data signals. The receiver includes a first clock and data recovery (CDR) circuit, a control circuit and a second CDR circuit. The first CDR circuit is configured to process the series of command signal to generate a clock signal. The control circuit, coupled to the first CDR circuit, is configured to generate a control signal according to the series of command signals and the clock signal received from the first CDR circuit. The second CDR circuit, coupled to the control circuit, is configured to process the series of data signals according to the control signal received from the control circuit.

Method for processing a sequence of digital signal samples comprising a first sub-sequence and a second sub-sequence, said method comprising: forming (106) a first block of samples comprising the first sub-sequence and a second block of samples comprising header samples followed by the second sub-sequence; demodulating (108) the first block of samples through a digital demodulator to produce a first block of symbols, and the second block of digital signal samples through a second digital demodulator to produce a second block of symbols, the second demodulator implementing a carrier synchronisation or symbol rate synchronisation starting with the header samples (E6-E9), which comprise samples in a number adapted in such a way that the synchronisation is effective before the second demodulator demodulates the second sub-sequence; and reconstructing (114) a sequence of symbols by concatenating the first symbol block with the second symbol block.

Method for processing a sequence of digital signal samples comprising a first sub-sequence and a second sub-sequence, said method comprising: forming (106) a first block of samples comprising the first sub-sequence and a second block of samples comprising header samples followed by the second sub-sequence; demodulating (108) the first block of samples through a digital demodulator to produce a first block of symbols, and the second block of digital signal samples through a second digital demodulator to produce a second block of symbols, the second demodulator implementing a carrier synchronisation or symbol rate synchronisation starting with the header samples (E6-E9), which comprise samples in a number adapted in such a way that the synchronisation is effective before the second demodulator demodulates the second sub-sequence; and reconstructing (114) a sequence of symbols by concatenating the first symbol block with the second symbol block.

The present invention discloses an image data transmission apparatus. The lock confirmation circuit receives an original signal having an original pulse width from the image data reception apparatus to generate an output signal. The image data transmission circuit determines that the image data reception apparatus locks a transmission frequency when an output pulse width is larger than a pulse threshold value to perform a synchronous image data transmission. The lock confirmation circuit sets the output pulse width to be a lengthened pulse width when a difference between the original pulse width and the pulse threshold value is smaller than a predetermined value and the original pulse width is not smaller than the pulse threshold value. The lock confirmation circuit sets the output pulse width to be a shortened pulse width when the difference is smaller than the predetermined value and the original pulse width is smaller than the pulse threshold value.

The present invention discloses an image data transmission apparatus. The lock confirmation circuit receives an original signal having an original pulse width from the image data reception apparatus to generate an output signal. The image data transmission circuit determines that the image data reception apparatus locks a transmission frequency when an output pulse width is larger than a pulse threshold value to perform a synchronous image data transmission. The lock confirmation circuit sets the output pulse width to be a lengthened pulse width when a difference between the original pulse width and the pulse threshold value is smaller than a predetermined value and the original pulse width is not smaller than the pulse threshold value. The lock confirmation circuit sets the output pulse width to be a shortened pulse width when the difference is smaller than the predetermined value and the original pulse width is smaller than the pulse threshold value.

Disclosed herein include a system and a method of synchronizing a slave device to a signal from a master device based on pulse width analysis. The pulse width analysis is a process to sample the signal at a sampling frequency of the slave device, determine varying pulse widths of the sampled signal, and determine frequency of an embedded master clock signal of the signal based on statistical analysis of the varying pulse widths. Advantageously, performing pulse width analysis allows synchronization of a slave device with the embedded master clock signal in a time and cost efficient manner. In one aspect, determining a frequency of the embedded master clock signal and adjusting an internal clock of the slave device according to the determined frequency is faster and more cost efficient than iteratively adjusting the internal clock based on feedback loop based circuitries.

A restraint control module is provided in this disclosure. The restraint control module is configured to communicate a sync pulse to a sensor. The control module may include a sync pulse driver circuit and a memory. The memory may store the waveform profile of a sync pulse. The sync pulse driver circuit generates a sync pulse in response to the waveform profile stored in the memory. The sync pulse may be transmitted to one or more sensors. The waveform profile stored in the memory may be derived from a sync pulse with reduced electro-magnetic emissions by applying spectrum analysis.

The present invention relates to a method for adapting a link using a polar-modulation (PQAM) constellation. It applies in particular to the communications in the sub-THz band, in which the oscillator of the receiver has phase fluctuations. In a PQAM-modulation constellation, the modulation symbols are distributed on concentric circles equidistant in the complex plane, each circle including the same number of symbols, the angular distribution of the symbols on a circle being uniform and identical regardless of the circle. The adaptation of the link is carried out by taking into account the thermal noise as well as the phase noise.

The present invention relates to a method for adapting a link using a polar-modulation (PQAM) constellation. It applies in particular to the communications in the sub-THz band, in which the oscillator of the receiver has phase fluctuations. In a PQAM-modulation constellation, the modulation symbols are distributed on concentric circles equidistant in the complex plane, each circle including the same number of symbols, the angular distribution of the symbols on a circle being uniform and identical regardless of the circle. The adaptation of the link is carried out by taking into account the thermal noise as well as the phase noise.

A method for synchronizing radio frequency carrier correction of dynamic radio frequency carriers is provided. The method includes receiving a carrier configuration from a carrier controller to modulate a carrier signal based on the carrier configuration and receiving a time reference and timestamped carrier configuration information from the carrier controller. The timestamped carrier configuration information includes a correlation between a plurality of timestamps and a plurality of carrier attributes. The method also includes synchronizing an internal clock of a RF correction preprocessor to the time reference, and receiving a modulated carrier signal from the RF modem. The method further includes generating a radio frequency correction set including a correction solution for each of a plurality of timeslots based on the timestamped carrier configuration information, and generating a corrected carrier signal based on applying the RF correction set to the modulated carrier signal at a coincident timeslot.